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Add parameter to disable CSR/interrupts

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Also disables timer in servant if CSR/interrupts are disabled
This commit is contained in:
Olof Kindgren
2019-12-01 20:54:54 +01:00
parent fca1527dd7
commit b48b02b8df
8 changed files with 137 additions and 62 deletions
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29
servant/servant.v
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@@ -7,6 +7,7 @@ module servant
parameter memfile = "zephyr_hello.hex";
parameter memsize = 8192;
parameter with_csr = 1;
wire timer_irq;
@@ -135,15 +136,22 @@ servant_arbiter servant_arbiter
.o_wb_rdt (wb_mem_rdt),
.o_wb_ack (wb_mem_ack));
servant_timer
#(.WIDTH (32))
timer
(.i_clk (wb_clk),
.o_irq (timer_irq),
.i_wb_cyc (wb_timer_cyc),
.i_wb_we (wb_timer_we) ,
.i_wb_dat (wb_timer_dat),
.o_wb_dat (wb_timer_rdt));
generate
if (with_csr) begin
servant_timer
#(.WIDTH (32))
timer
(.i_clk (wb_clk),
.o_irq (timer_irq),
.i_wb_cyc (wb_timer_cyc),
.i_wb_we (wb_timer_we) ,
.i_wb_dat (wb_timer_dat),
.o_wb_dat (wb_timer_rdt));
end else begin
assign wb_timer_rdt = 32'd0;
assign timer_irq = 1'b0;
end
endgenerate
servant_gpio gpio
(.i_wb_clk (wb_clk),
@@ -154,7 +162,8 @@ servant_arbiter servant_arbiter
.o_gpio (q));
serv_rf_top
#(.RESET_PC (32'h0000_0000))
#(.RESET_PC (32'h0000_0000),
.WITH_CSR (with_csr))
cpu
(
.clk (wb_clk),