From c1b84716782b07cf5136f072a873abe8e283b7b1 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Fri, 9 Oct 2020 23:43:30 +0200 Subject: [PATCH] Add reset_strategy parameter The reset_strategy parameter controls how much reset to apply to SERV. It can be set to MINI for the default behaviour, or NONE to only apply reset where absolutely needed and rely on POR to clear FFs --- rtl/serv_ctrl.v | 11 +++++++++-- rtl/serv_rf_ram_if.v | 10 +++++++--- rtl/serv_rf_top.v | 10 ++++++++++ rtl/serv_state.v | 13 +++++++++---- rtl/serv_top.v | 5 ++++- servant/servant.v | 4 +++- serving/serving.v | 5 ++++- 7 files changed, 46 insertions(+), 12 deletions(-) diff --git a/rtl/serv_ctrl.v b/rtl/serv_ctrl.v index 108fd2a..c6f5f5f 100644 --- a/rtl/serv_ctrl.v +++ b/rtl/serv_ctrl.v @@ -1,5 +1,6 @@ `default_nettype none module serv_ctrl + #(parameter RESET_STRATEGY = "MINI") ( input wire clk, input wire i_rst, @@ -68,6 +69,8 @@ module serv_ctrl assign o_ibus_cyc = en_pc_r & !i_pc_en; + initial if (RESET_STRATEGY == "NONE") o_ibus_adr = RESET_PC; + always @(posedge clk) begin pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy; pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy; @@ -75,8 +78,12 @@ module serv_ctrl if (o_ibus_cyc & i_ibus_ack | i_pc_en | i_rst) en_pc_r <= i_pc_en | i_rst; - if (i_pc_en | i_rst) begin - o_ibus_adr <= i_rst ? RESET_PC : {new_pc, o_ibus_adr[31:1]}; + if (RESET_STRATEGY == "NONE") begin + if (i_pc_en) + o_ibus_adr <= {new_pc, o_ibus_adr[31:1]}; + end else begin + if (i_pc_en | i_rst) + o_ibus_adr <= i_rst ? RESET_PC : {new_pc, o_ibus_adr[31:1]}; end end endmodule diff --git a/rtl/serv_rf_ram_if.v b/rtl/serv_rf_ram_if.v index 64da74c..f7b47da 100644 --- a/rtl/serv_rf_ram_if.v +++ b/rtl/serv_rf_ram_if.v @@ -1,6 +1,7 @@ `default_nettype none module serv_rf_ram_if #(parameter width=8, + parameter reset_strategy="MINI", parameter csr_regs=4, parameter depth=32*(32+csr_regs)/width, parameter l2w = $clog2(width)) @@ -97,7 +98,8 @@ module serv_rf_ram_if wgo <= 1'b0; if (i_rst) begin - wcnt <= 5'd0; + if (reset_strategy != "NONE") + wcnt <= 5'd0; end end @@ -151,8 +153,10 @@ module serv_rf_ram_if rdata0 <= i_rdata; if (i_rst) begin - rgnt <= 1'b0; - rreq_r <= 1'b0; + if (reset_strategy != "NONE") begin + rgnt <= 1'b0; + rreq_r <= 1'b0; + end end end diff --git a/rtl/serv_rf_top.v b/rtl/serv_rf_top.v index ef0ae41..e84ac36 100644 --- a/rtl/serv_rf_top.v +++ b/rtl/serv_rf_top.v @@ -2,6 +2,14 @@ module serv_rf_top #(parameter RESET_PC = 32'd0, + + /* Amount of reset applied to design + "NONE" : No reset at all. Relies on a POR to set correct initialization + values and that core isn't reset during runtime + "MINI" : Standard setting. Resets the minimal amount of FFs needed to + restart execution from the instruction at RESET_PC + */ + parameter RESET_STRATEGY = "MINI", parameter WITH_CSR = 1, parameter RF_WIDTH = 2, parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH)) @@ -68,6 +76,7 @@ module serv_rf_top serv_rf_ram_if #(.width (RF_WIDTH), + .reset_strategy (RESET_STRATEGY), .csr_regs (CSR_REGS)) rf_ram_if (.i_clk (clk), @@ -104,6 +113,7 @@ module serv_rf_top serv_top #(.RESET_PC (RESET_PC), + .RESET_STRATEGY (RESET_STRATEGY), .WITH_CSR (WITH_CSR)) cpu ( diff --git a/rtl/serv_state.v b/rtl/serv_state.v index 6c2e845..b461fd7 100644 --- a/rtl/serv_state.v +++ b/rtl/serv_state.v @@ -1,4 +1,5 @@ module serv_state + #(parameter RESET_STRATEGY = "MINI") ( input wire i_clk, input wire i_rst, @@ -96,6 +97,8 @@ module serv_state //Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting assign o_bufreg_hold = !o_cnt_en & (stage_two_req | ~i_shift_op); + initial if (RESET_STRATEGY == "NONE") o_cnt_r = 4'b0001; + always @(posedge i_clk) begin if (o_cnt_done) o_ctrl_jump <= o_init & take_branch; @@ -125,10 +128,12 @@ module serv_state o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]}; if (i_rst) begin - o_cnt <= 3'd0; - stage_two_pending <= 1'b0; - o_ctrl_jump <= 1'b0; - o_cnt_r <= 4'b0001; + if (RESET_STRATEGY != "NONE") begin + o_cnt <= 3'd0; + stage_two_pending <= 1'b0; + o_ctrl_jump <= 1'b0; + o_cnt_r <= 4'b0001; + end end end diff --git a/rtl/serv_top.v b/rtl/serv_top.v index 748a7f1..a50e77c 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -2,6 +2,7 @@ module serv_top #(parameter WITH_CSR = 1, + parameter RESET_STRATEGY = "MINI", parameter RESET_PC = 32'd0) ( input wire clk, @@ -155,7 +156,8 @@ module serv_top wire [1:0] lsb; serv_state - #(.WITH_CSR (WITH_CSR)) + #(.RESET_STRATEGY (RESET_STRATEGY), + .WITH_CSR (WITH_CSR)) state ( .i_clk (clk), @@ -296,6 +298,7 @@ module serv_top serv_ctrl #(.RESET_PC (RESET_PC), + .RESET_STRATEGY (RESET_STRATEGY), .WITH_CSR (WITH_CSR)) ctrl ( diff --git a/servant/servant.v b/servant/servant.v index a5e6424..d9426c8 100644 --- a/servant/servant.v +++ b/servant/servant.v @@ -7,6 +7,7 @@ module servant parameter memfile = "zephyr_hello.hex"; parameter memsize = 8192; + parameter reset_strategy = "MINI"; parameter sim = 0; parameter with_csr = 1; @@ -76,7 +77,7 @@ module servant servant_mux #(sim) servant_mux ( .i_clk (wb_clk), - .i_rst (wb_rst), + .i_rst (wb_rst & (reset_strategy != "NONE")), .i_wb_cpu_adr (wb_dbus_adr), .i_wb_cpu_dat (wb_dbus_dat), .i_wb_cpu_sel (wb_dbus_sel), @@ -143,6 +144,7 @@ module servant serv_rf_top #(.RESET_PC (32'h0000_0000), + .RESET_STRATEGY (reset_strategy), .WITH_CSR (with_csr)) cpu ( diff --git a/serving/serving.v b/serving/serving.v index 374bab4..2151862 100644 --- a/serving/serving.v +++ b/serving/serving.v @@ -34,6 +34,7 @@ module serving parameter memfile = ""; parameter memsize = 8192; + parameter RESET_STRATEGY = "NONE"; parameter WITH_CSR = 1; localparam regs = 32+WITH_CSR*4; @@ -104,7 +105,7 @@ module serving serving_mux mux (.i_clk (i_clk), - .i_rst (i_rst), + .i_rst (i_rst & (RESET_STRATEGY != "NONE")), .i_wb_cpu_adr (wb_dbus_adr), .i_wb_cpu_dat (wb_dbus_dat), @@ -168,6 +169,7 @@ module serving serv_rf_ram_if #(.width (rf_width), + .reset_strategy (RESET_STRATEGY), .csr_regs (WITH_CSR*4)) rf_ram_if (.i_clk (i_clk), @@ -193,6 +195,7 @@ module serving serv_top #(.RESET_PC (32'h0000_0000), + .RESET_STRATEGY (RESET_STRATEGY), .WITH_CSR (WITH_CSR)) cpu (