diff --git a/firmware.hex b/firmware.hex
index c0e37f1..b2484b6 100644
--- a/firmware.hex
+++ b/firmware.hex
@@ -46,7 +46,7 @@
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diff --git a/picorv32_firmware/Makefile b/picorv32_firmware/Makefile
new file mode 100644
index 0000000..db0a301
--- /dev/null
+++ b/picorv32_firmware/Makefile
@@ -0,0 +1,179 @@
+
+RISCV_GNU_TOOLCHAIN_GIT_REVISION = c3ad555
+RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX = /opt/riscv32
+
+SHELL = bash
+TEST_OBJS = $(addsuffix .o,$(basename $(wildcard tests/*.S)))
+FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/sieve.o firmware/multest.o firmware/stats.o
+GCC_WARNS  = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
+GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
+TOOLCHAIN_PREFIX = $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i/bin/riscv32-unknown-elf-
+
+# Add things like "export http_proxy=... https_proxy=..." here
+GIT_ENV = true
+
+test: testbench.vvp firmware/firmware.hex
+	vvp -N $<
+
+test_vcd: testbench.vvp firmware/firmware.hex
+	vvp -N $< +vcd +trace +noerror
+
+test_rvf: testbench_rvf.vvp firmware/firmware.hex
+	vvp -N $< +vcd +trace +noerror
+
+test_wb: testbench_wb.vvp firmware/firmware.hex
+	vvp -N $<
+
+test_wb_vcd: testbench_wb.vvp firmware/firmware.hex
+	vvp -N $< +vcd +trace +noerror
+
+test_ez: testbench_ez.vvp
+	vvp -N $<
+
+test_ez_vcd: testbench_ez.vvp
+	vvp -N $< +vcd
+
+test_sp: testbench_sp.vvp firmware/firmware.hex
+	vvp -N $<
+
+test_axi: testbench.vvp firmware/firmware.hex
+	vvp -N $< +axi_test
+
+test_synth: testbench_synth.vvp firmware/firmware.hex
+	vvp -N $<
+
+test_verilator: testbench_verilator firmware/firmware.hex
+	./testbench_verilator
+
+testbench.vvp: testbench.v picorv32.v
+	iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
+	chmod -x $@
+
+testbench_rvf.vvp: testbench.v picorv32.v rvfimon.v
+	iverilog -o $@ -D RISCV_FORMAL $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
+	chmod -x $@
+
+testbench_wb.vvp: testbench_wb.v picorv32.v
+	iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
+	chmod -x $@
+
+testbench_ez.vvp: testbench_ez.v picorv32.v
+	iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
+	chmod -x $@
+
+testbench_sp.vvp: testbench.v picorv32.v
+	iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST $^
+	chmod -x $@
+
+testbench_synth.vvp: testbench.v synth.v
+	iverilog -o $@ -DSYNTH_TEST $^
+	chmod -x $@
+
+testbench_verilator: testbench.v picorv32.v
+	verilator --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench.v picorv32.v testbench.cc \
+			$(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) --Mdir testbench_verilator_dir
+	$(MAKE) -C testbench_verilator_dir -f Vpicorv32_wrapper.mk
+	cp testbench_verilator_dir/Vpicorv32_wrapper testbench_verilator
+
+check: check-yices
+
+check-%: check.smt2
+	yosys-smtbmc -s $(subst check-,,$@) -t 30 --dump-vcd check.vcd check.smt2
+	yosys-smtbmc -s $(subst check-,,$@) -t 25 --dump-vcd check.vcd -i check.smt2
+
+check.smt2: picorv32.v
+	yosys -v2 -p 'read_verilog -formal picorv32.v' \
+	          -p 'prep -top picorv32 -nordff' \
+		  -p 'assertpmux -noinit; opt -fast' \
+		  -p 'write_smt2 -wires check.smt2'
+
+synth.v: picorv32.v scripts/yosys/synth_sim.ys
+	yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys
+
+firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py
+	python3 firmware/makehex.py $< 16384 > $@
+
+firmware/firmware.bin: firmware/firmware.elf
+	$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
+	chmod -x $@
+
+firmware/firmware.elf: $(FIRMWARE_OBJS) $(TEST_OBJS) firmware/sections.lds
+	$(TOOLCHAIN_PREFIX)gcc -Os -ffreestanding -nostdlib -o $@ \
+		-Wl,-Bstatic,-T,firmware/sections.lds,-Map,firmware/firmware.map,--strip-debug \
+		$(FIRMWARE_OBJS) $(TEST_OBJS) -lgcc
+	chmod -x $@
+
+firmware/start.o: firmware/start.S
+	$(TOOLCHAIN_PREFIX)gcc -c -march=rv32i$(subst C,c,$(COMPRESSED_ISA)) -o $@ $<
+
+firmware/%.o: firmware/%.c
+	$(TOOLCHAIN_PREFIX)gcc -c -march=rv32i$(subst C,c,$(COMPRESSED_ISA)) -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
+
+tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
+	$(TOOLCHAIN_PREFIX)gcc -c -march=rv32i -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
+		-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
+
+download-tools:
+	sudo bash -c 'set -ex; mkdir -p /var/cache/distfiles; $(GIT_ENV); \
+	$(foreach REPO,riscv-gnu-toolchain riscv-binutils-gdb riscv-dejagnu riscv-gcc riscv-glibc riscv-newlib riscv-qemu, \
+		if ! test -d /var/cache/distfiles/$(REPO).git; then rm -rf /var/cache/distfiles/$(REPO).git.part; \
+			git clone --bare https://github.com/riscv/$(REPO) /var/cache/distfiles/$(REPO).git.part; \
+			mv /var/cache/distfiles/$(REPO).git.part /var/cache/distfiles/$(REPO).git; else \
+			(cd /var/cache/distfiles/$(REPO).git; git fetch https://github.com/riscv/$(REPO)); fi;)'
+
+define build_tools_template
+build-$(1)-tools:
+	@read -p "This will remove all existing data from $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)). Type YES to continue: " reply && [[ "$$$$reply" == [Yy][Ee][Ss] || "$$$$reply" == [Yy] ]]
+	sudo bash -c "set -ex; rm -rf $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); mkdir -p $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); chown $$$${USER}: $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1))"
+	+$(MAKE) build-$(1)-tools-bh
+
+build-$(1)-tools-bh:
+	+set -ex; $(GIT_ENV); \
+	if [ -d /var/cache/distfiles/riscv-gnu-toolchain.git ]; then reference_riscv_gnu_toolchain="--reference /var/cache/distfiles/riscv-gnu-toolchain.git"; else reference_riscv_gnu_toolchain=""; fi; \
+	if [ -d /var/cache/distfiles/riscv-binutils-gdb.git ]; then reference_riscv_binutils_gdb="--reference /var/cache/distfiles/riscv-binutils-gdb.git"; else reference_riscv_binutils_gdb=""; fi; \
+	if [ -d /var/cache/distfiles/riscv-dejagnu.git ]; then reference_riscv_dejagnu="--reference /var/cache/distfiles/riscv-dejagnu.git"; else reference_riscv_dejagnu=""; fi; \
+	if [ -d /var/cache/distfiles/riscv-gcc.git ]; then reference_riscv_gcc="--reference /var/cache/distfiles/riscv-gcc.git"; else reference_riscv_gcc=""; fi; \
+	if [ -d /var/cache/distfiles/riscv-glibc.git ]; then reference_riscv_glibc="--reference /var/cache/distfiles/riscv-glibc.git"; else reference_riscv_glibc=""; fi; \
+	if [ -d /var/cache/distfiles/riscv-newlib.git ]; then reference_riscv_newlib="--reference /var/cache/distfiles/riscv-newlib.git"; else reference_riscv_newlib=""; fi; \
+	if [ -d /var/cache/distfiles/riscv-qemu.git ]; then reference_riscv_qemu="--reference /var/cache/distfiles/riscv-qemu.git"; else reference_riscv_qemu=""; fi; \
+	rm -rf riscv-gnu-toolchain-$(1); git clone $$$$reference_riscv_gnu_toolchain https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-$(1); \
+	cd riscv-gnu-toolchain-$(1); git checkout $(RISCV_GNU_TOOLCHAIN_GIT_REVISION); \
+	git submodule update --init $$$$reference_riscv_binutils_gdb riscv-binutils; \
+	git submodule update --init $$$$reference_riscv_binutils_gdb riscv-gdb; \
+	git submodule update --init $$$$reference_riscv_dejagnu riscv-dejagnu; \
+	git submodule update --init $$$$reference_riscv_gcc riscv-gcc; \
+	git submodule update --init $$$$reference_riscv_glibc riscv-glibc; \
+	git submodule update --init $$$$reference_riscv_newlib riscv-newlib; \
+	git submodule update --init $$$$reference_riscv_qemu riscv-qemu; \
+	mkdir build; cd build; ../configure --with-arch=$(2) --prefix=$(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); make
+
+.PHONY: build-$(1)-tools
+endef
+
+$(eval $(call build_tools_template,riscv32i,rv32i))
+$(eval $(call build_tools_template,riscv32ic,rv32ic))
+$(eval $(call build_tools_template,riscv32im,rv32im))
+$(eval $(call build_tools_template,riscv32imc,rv32imc))
+
+build-tools:
+	@echo "This will remove all existing data from $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i, $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)ic, $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)im, and $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)imc."
+	@read -p "Type YES to continue: " reply && [[ "$$reply" == [Yy][Ee][Ss] || "$$reply" == [Yy] ]]
+	sudo bash -c "set -ex; rm -rf $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}; mkdir -p $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}; chown $${USER}: $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}"
+	+$(MAKE) build-riscv32i-tools-bh
+	+$(MAKE) build-riscv32ic-tools-bh
+	+$(MAKE) build-riscv32im-tools-bh
+	+$(MAKE) build-riscv32imc-tools-bh
+
+toc:
+	gawk '/^-+$$/ { y=tolower(x); gsub("[^a-z0-9]+", "-", y); gsub("-$$", "", y); printf("- [%s](#%s)\n", x, y); } { x=$$0; }' README.md
+
+clean:
+	rm -rf riscv-gnu-toolchain-riscv32i riscv-gnu-toolchain-riscv32ic \
+		riscv-gnu-toolchain-riscv32im riscv-gnu-toolchain-riscv32imc
+	rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
+		firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
+		testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench_ez.vvp \
+		testbench_rvf.vvp testbench_wb.vvp testbench.vcd testbench.trace \
+		testbench_verilator testbench_verilator_dir
+
+.PHONY: test test_vcd test_sp test_axi test_wb test_wb_vcd test_ez test_ez_vcd test_synth download-tools build-tools toc clean
diff --git a/picorv32_firmware/firmware/firmware.bin b/picorv32_firmware/firmware/firmware.bin
deleted file mode 100644
index e7d75de..0000000
Binary files a/picorv32_firmware/firmware/firmware.bin and /dev/null differ
diff --git a/picorv32_firmware/firmware/firmware.elf b/picorv32_firmware/firmware/firmware.elf
index 31397ad..75e5569 100644
Binary files a/picorv32_firmware/firmware/firmware.elf and b/picorv32_firmware/firmware/firmware.elf differ
diff --git a/picorv32_firmware/firmware/firmware.hex b/picorv32_firmware/firmware/firmware.hex
index c0e37f1..b2484b6 100644
--- a/picorv32_firmware/firmware/firmware.hex
+++ b/picorv32_firmware/firmware/firmware.hex
@@ -46,7 +46,7 @@
 00000537
 16050513
 0000c58b
-638000ef
+5b8000ef
 00050093
 0000a103
 0201200b
@@ -279,146 +279,121 @@
 00000f93
 3e800093
 0a00e00b
-0080706f
+7850506f
 3e800093
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-6790406f
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 3e800093
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-05c0506f
+21d0406f
 3e800093
 0a00e00b
-7b90106f
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 0a00e00b
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 3e800093
 0a00e00b
-49c0606f
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 3e800093
 0a00e00b
-75c0606f
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 3e800093
 0a00e00b
-0a40806f
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 3e800093
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 3e800093
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 0a00e00b
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-12d0306f
-3e800093
-0a00e00b
-3a50706f
-3e800093
-0a00e00b
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+0580706f
 00010137
 deadc1b7
 eef18193
 00018213
-614000ef
-7cc000ef
-321000ef
+5f4000ef
+23d000ef
 10000537
 04400593
 04f00613
@@ -435,14 +410,7 @@ eef18193
 d1558593
 00b52023
 00100073
-02b50533
-00008067
-02b51533
-00008067
-02b52533
-00008067
-02b53533
-00008067
+00000000
 00000000
 fb010113
 04912223
@@ -478,14 +446,14 @@ ffd70793
 ffda0793
 00f037b3
 04d78863
-0000b537
-dc450513
+00009537
+1d450513
 354000ef
 00092503
 00800593
 3e4000ef
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-e0050513
+00009537
+21050513
 33c000ef
 00300793
 00800593
@@ -493,28 +461,28 @@ e0050513
 00400593
 00040513
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-e4850513
+00009537
+25850513
 318000ef
 00100073
 0109f793
 00078a63
-0000b737
-f2c72783
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 00178793
-f2f72623
+32f72e23
 0209f793
 00078a63
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-f2872783
+00009737
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 00178793
-f2f72423
+32f72c23
 0019f793
 00078a63
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-f2472783
+00009737
+33472783
 00178793
-f2f72223
+32f72a23
 1c048463
 00092783
 0017f713
@@ -528,11 +496,11 @@ ffd78a13
 002a5783
 01079793
 00f4e4b3
-0000b437
-e4840513
+00009437
+25840513
 28c000ef
-0000bab7
-e0ca8513
+00009ab7
+21ca8513
 280000ef
 0029f793
 02078e63
@@ -542,24 +510,24 @@ e0ca8513
 000097b7
 00278793
 1af49063
-0000b537
-e4c50513
+00009537
+25c50513
 254000ef
 00800593
 000a0513
 2e4000ef
-e4840513
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 240000ef
 0049f993
 04098663
-0000b537
-e8c50513
+00009537
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 22c000ef
 00800593
 000a0513
 2bc000ef
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-e8450513
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 214000ef
 0034f793
 00300713
@@ -568,23 +536,23 @@ e8450513
 00800593
 00048513
 294000ef
-e4840513
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 1f0000ef
-0000bbb7
+00009bb7
 00000a13
 00900c93
 01300d13
-0000bdb7
-dbcb8b93
+00009db7
+1ccb8b93
 002a1993
-e4840793
+25840793
 000a0493
 013909b3
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diff --git a/picorv32_firmware/firmware/firmware.map b/picorv32_firmware/firmware/firmware.map
deleted file mode 100644
index c87d310..0000000
--- a/picorv32_firmware/firmware/firmware.map
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- .debug_aranges
-                0x0000000000000000       0x20 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(div.o)
- .debug_str     0x0000000000000000       0x9a /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(div.o)
-
-Memory Configuration
-
-Name             Origin             Length             Attributes
-mem              0x0000000000000000 0x000000000000c000
-*default*        0x0000000000000000 0xffffffffffffffff
-
-Linker script and memory map
-
-
-.memory         0x0000000000000000     0xb080
-                0x0000000000000000                . = 0x0
- start*(.text)
- *(.text)
- .text          0x0000000000000000      0x6f8 firmware/start.o
-                0x0000000000000468                lui_ret
-                0x0000000000000474                auipc_ret
-                0x0000000000000480                j_ret
-                0x000000000000048c                jal_ret
-                0x0000000000000498                jalr_ret
-                0x00000000000004a4                beq_ret
-                0x00000000000004b0                bne_ret
-                0x00000000000004bc                blt_ret
-                0x00000000000004c8                bge_ret
-                0x00000000000004d4                bltu_ret
-                0x00000000000004e0                bgeu_ret
-                0x00000000000004ec                lb_ret
-                0x00000000000004f8                lh_ret
-                0x0000000000000504                lw_ret
-                0x0000000000000510                lbu_ret
-                0x000000000000051c                lhu_ret
-                0x0000000000000528                sb_ret
-                0x0000000000000534                sh_ret
-                0x0000000000000540                sw_ret
-                0x000000000000054c                addi_ret
-                0x0000000000000558                slti_ret
-                0x0000000000000564                xori_ret
-                0x0000000000000570                ori_ret
-                0x000000000000057c                andi_ret
-                0x0000000000000588                slli_ret
-                0x0000000000000594                srli_ret
-                0x00000000000005a0                srai_ret
-                0x00000000000005ac                add_ret
-                0x00000000000005b8                sub_ret
-                0x00000000000005c4                sll_ret
-                0x00000000000005d0                slt_ret
-                0x00000000000005dc                xor_ret
-                0x00000000000005e8                srl_ret
-                0x00000000000005f4                sra_ret
-                0x0000000000000600                or_ret
-                0x000000000000060c                and_ret
-                0x0000000000000618                mulh_ret
-                0x0000000000000624                mulhsu_ret
-                0x0000000000000630                mulhu_ret
-                0x000000000000063c                mul_ret
-                0x0000000000000648                div_ret
-                0x0000000000000654                divu_ret
-                0x0000000000000660                rem_ret
-                0x000000000000066c                remu_ret
-                0x0000000000000678                simple_ret
-                0x00000000000006d4                hard_mul
-                0x00000000000006dc                hard_mulh
-                0x00000000000006e4                hard_mulhsu
-                0x00000000000006ec                hard_mulhu
- .text          0x00000000000006f8      0x3d8 firmware/irq.o
-                0x00000000000006f8                irq
- .text          0x0000000000000ad0       0xe0 firmware/print.o
-                0x0000000000000ad0                print_chr
-                0x0000000000000adc                print_str
-                0x0000000000000af8                print_dec
-                0x0000000000000b78                print_hex
- .text          0x0000000000000bb0      0x280 firmware/sieve.o
-                0x0000000000000c9c                sieve
- .text          0x0000000000000e30      0x2a8 firmware/multest.o
-                0x0000000000000e58                multest
- .text          0x00000000000010d8      0x19c firmware/stats.o
-                0x00000000000011b0                stats
- .text          0x0000000000001274      0x268 tests/xori.o
-                0x0000000000001274                xori
- .text          0x00000000000014dc      0x544 tests/or.o
-                0x00000000000014dc                or
- .text          0x0000000000001a20      0x540 tests/xor.o
-                0x0000000000001a20                xor
- .text          0x0000000000001f60      0x540 tests/sub.o
-                0x0000000000001f60                sub
- .text          0x00000000000024a0      0x2cc tests/lb.o
-                0x00000000000024a0                lb
- .text          0x000000000000276c      0x2ec tests/lh.o
-                0x000000000000276c                lh
- .text          0x0000000000002a58      0x63c tests/srl.o
-                0x0000000000002a58                srl
- .text          0x0000000000003094      0x340 tests/blt.o
-                0x0000000000003094                blt
- .text          0x00000000000033d4      0x538 tests/and.o
-                0x00000000000033d4                and
- .text          0x000000000000390c      0x33c tests/srai.o
-                0x000000000000390c                srai
- .text          0x0000000000003c48      0x340 tests/beq.o
-                0x0000000000003c48                beq
- .text          0x0000000000003f88      0x15c tests/rem.o
-                0x0000000000003f88                rem
- .text          0x00000000000040e4      0x30c tests/addi.o
-                0x00000000000040e4                addi
- .text          0x00000000000043f0      0x548 tests/mul.o
-                0x00000000000043f0                mul
- .text          0x0000000000004938      0x164 tests/divu.o
-                0x0000000000004938                divu
- .text          0x0000000000004a9c      0x504 tests/sw.o
-                0x0000000000004a9c                sw
- .text          0x0000000000004fa0      0x344 tests/bne.o
-                0x0000000000004fa0                bne
- *fill*         0x00000000000052e4        0x4 
- .text          0x00000000000052e8       0xcc tests/auipc.o
-                0x00000000000052e8                auipc
- .text          0x00000000000053b4      0x184 tests/jalr.o
-                0x00000000000053b4                jalr
- .text          0x0000000000005538      0x3d8 tests/bgeu.o
-                0x0000000000005538                bgeu
- .text          0x0000000000005910      0x30c tests/lw.o
-                0x0000000000005910                lw
- .text          0x0000000000005c1c      0x54c tests/mulhu.o
-                0x0000000000005c1c                mulhu
- .text          0x0000000000006168      0x2f8 tests/slti.o
-                0x0000000000006168                slti
- .text          0x0000000000006460      0x548 tests/slt.o
-                0x0000000000006460                slt
- .text          0x00000000000069a8      0x2cc tests/lbu.o
-                0x00000000000069a8                lbu
- .text          0x0000000000006c74      0x300 tests/lhu.o
-                0x0000000000006c74                lhu
- .text          0x0000000000006f74      0x4f8 tests/sh.o
-                0x0000000000006f74                sh
- .text          0x000000000000746c       0xe0 tests/lui.o
-                0x000000000000746c                lui
- .text          0x000000000000754c      0x378 tests/bltu.o
-                0x000000000000754c                bltu
- .text          0x00000000000078c4      0x5ec tests/sll.o
-                0x00000000000078c4                sll
- .text          0x0000000000007eb0       0x54 tests/simple.o
-                0x0000000000007eb0                simple
- .text          0x0000000000007f04      0x308 tests/slli.o
-                0x0000000000007f04                slli
- .text          0x000000000000820c      0x160 tests/remu.o
-                0x000000000000820c                remu
- .text          0x000000000000836c      0x25c tests/ori.o
-                0x000000000000836c                ori
- .text          0x00000000000085c8      0x474 tests/sb.o
-                0x00000000000085c8                sb
- .text          0x0000000000008a3c       0xd8 tests/jal.o
-                0x0000000000008a3c                jal
- .text          0x0000000000008b14      0x560 tests/add.o
-                0x0000000000008b14                add
- .text          0x0000000000009074       0xbc tests/j.o
-                0x0000000000009074                j
- .text          0x0000000000009130      0x244 tests/andi.o
-                0x0000000000009130                andi
- .text          0x0000000000009374      0x61c tests/sra.o
-                0x0000000000009374                sra
- .text          0x0000000000009990      0x3a0 tests/bge.o
-                0x0000000000009990                bge
- .text          0x0000000000009d30      0x15c tests/div.o
-                0x0000000000009d30                div
- .text          0x0000000000009e8c      0x54c tests/mulh.o
-                0x0000000000009e8c                mulh
- .text          0x000000000000a3d8      0x54c tests/mulhsu.o
-                0x000000000000a3d8                mulhsu
- .text          0x000000000000a924      0x338 tests/srli.o
-                0x000000000000a924                srli
- .text          0x000000000000ac5c       0x24 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(muldi3.o)
-                0x000000000000ac5c                __mulsi3
- .text          0x000000000000ac80       0x88 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(multi3.o)
-                0x000000000000ac80                __muldi3
- .text          0x000000000000ad08       0xb4 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(div.o)
-                0x000000000000ad08                __divsi3
-                0x000000000000ad10                __udivsi3
-                0x000000000000ad58                __umodsi3
-                0x000000000000ad8c                __modsi3
- *(*)
- .data          0x000000000000adbc        0x0 firmware/start.o
- .bss           0x000000000000adbc        0x0 firmware/start.o
- .rela.text     0x000000000000adbc        0x0 firmware/start.o
- .data          0x000000000000adbc        0x0 firmware/irq.o
- .bss           0x000000000000adbc        0x0 firmware/irq.o
- .rodata.str1.4
-                0x000000000000adbc      0x167 firmware/irq.o
-                                        0x16b (size before relaxing)
- *fill*         0x000000000000af23        0x1 
- .sbss          0x000000000000af24        0xc firmware/irq.o
- .comment       0x000000000000af30       0x11 firmware/irq.o
-                                         0x12 (size before relaxing)
- .data          0x000000000000af41        0x0 firmware/print.o
- .bss           0x000000000000af41        0x0 firmware/print.o
- *fill*         0x000000000000af41        0x3 
- .rodata.str1.4
-                0x000000000000af44       0x11 firmware/print.o
- .comment       0x000000000000af55       0x12 firmware/print.o
- .data          0x000000000000af55        0x0 firmware/sieve.o
- .bss           0x000000000000af55        0x0 firmware/sieve.o
- *fill*         0x000000000000af55        0x3 
- .rodata.str1.4
-                0x000000000000af58       0x40 firmware/sieve.o
- .sbss          0x000000000000af98        0xc firmware/sieve.o
- .comment       0x000000000000afa4       0x12 firmware/sieve.o
- .data          0x000000000000afa4        0x0 firmware/multest.o
- .bss           0x000000000000afa4        0x0 firmware/multest.o
- .rodata.str1.4
-                0x000000000000afa4       0x2c firmware/multest.o
-                                         0x31 (size before relaxing)
- .sdata         0x000000000000afd0        0x4 firmware/multest.o
- .comment       0x000000000000afd4       0x12 firmware/multest.o
- .data          0x000000000000afd4        0x0 firmware/stats.o
- .bss           0x000000000000afd4        0x0 firmware/stats.o
- .rodata.str1.4
-                0x000000000000afd4       0x3c firmware/stats.o
-                                         0x3e (size before relaxing)
- .comment       0x000000000000b010       0x12 firmware/stats.o
- .data          0x000000000000b010        0x0 tests/xori.o
- .bss           0x000000000000b010        0x0 tests/xori.o
- .data          0x000000000000b010        0x0 tests/or.o
- .bss           0x000000000000b010        0x0 tests/or.o
- .data          0x000000000000b010        0x0 tests/xor.o
- .bss           0x000000000000b010        0x0 tests/xor.o
- .data          0x000000000000b010        0x0 tests/sub.o
- .bss           0x000000000000b010        0x0 tests/sub.o
- .data          0x000000000000b010        0x4 tests/lb.o
- .bss           0x000000000000b014        0x0 tests/lb.o
- .data          0x000000000000b014        0x8 tests/lh.o
- .bss           0x000000000000b01c        0x0 tests/lh.o
- .data          0x000000000000b01c        0x0 tests/srl.o
- .bss           0x000000000000b01c        0x0 tests/srl.o
- .data          0x000000000000b01c        0x0 tests/blt.o
- .bss           0x000000000000b01c        0x0 tests/blt.o
- .data          0x000000000000b01c        0x0 tests/and.o
- .bss           0x000000000000b01c        0x0 tests/and.o
- .data          0x000000000000b01c        0x0 tests/srai.o
- .bss           0x000000000000b01c        0x0 tests/srai.o
- .data          0x000000000000b01c        0x0 tests/beq.o
- .bss           0x000000000000b01c        0x0 tests/beq.o
- .data          0x000000000000b01c        0x0 tests/rem.o
- .bss           0x000000000000b01c        0x0 tests/rem.o
- .data          0x000000000000b01c        0x0 tests/addi.o
- .bss           0x000000000000b01c        0x0 tests/addi.o
- .data          0x000000000000b01c        0x0 tests/mul.o
- .bss           0x000000000000b01c        0x0 tests/mul.o
- .data          0x000000000000b01c        0x0 tests/divu.o
- .bss           0x000000000000b01c        0x0 tests/divu.o
- .data          0x000000000000b01c       0x28 tests/sw.o
- .bss           0x000000000000b044        0x0 tests/sw.o
- .data          0x000000000000b044        0x0 tests/bne.o
- .bss           0x000000000000b044        0x0 tests/bne.o
- .data          0x000000000000b044        0x0 tests/auipc.o
- .bss           0x000000000000b044        0x0 tests/auipc.o
- .data          0x000000000000b044        0x0 tests/jalr.o
- .bss           0x000000000000b044        0x0 tests/jalr.o
- .data          0x000000000000b044        0x0 tests/bgeu.o
- .bss           0x000000000000b044        0x0 tests/bgeu.o
- .data          0x000000000000b044       0x10 tests/lw.o
- .bss           0x000000000000b054        0x0 tests/lw.o
- .data          0x000000000000b054        0x0 tests/mulhu.o
- .bss           0x000000000000b054        0x0 tests/mulhu.o
- .data          0x000000000000b054        0x0 tests/slti.o
- .bss           0x000000000000b054        0x0 tests/slti.o
- .data          0x000000000000b054        0x0 tests/slt.o
- .bss           0x000000000000b054        0x0 tests/slt.o
- .data          0x000000000000b054        0x4 tests/lbu.o
- .bss           0x000000000000b058        0x0 tests/lbu.o
- .data          0x000000000000b058        0x8 tests/lhu.o
- .bss           0x000000000000b060        0x0 tests/lhu.o
- .data          0x000000000000b060       0x14 tests/sh.o
- .bss           0x000000000000b074        0x0 tests/sh.o
- .data          0x000000000000b074        0x0 tests/lui.o
- .bss           0x000000000000b074        0x0 tests/lui.o
- .data          0x000000000000b074        0x0 tests/bltu.o
- .bss           0x000000000000b074        0x0 tests/bltu.o
- .data          0x000000000000b074        0x0 tests/sll.o
- .bss           0x000000000000b074        0x0 tests/sll.o
- .data          0x000000000000b074        0x0 tests/simple.o
- .bss           0x000000000000b074        0x0 tests/simple.o
- .data          0x000000000000b074        0x0 tests/slli.o
- .bss           0x000000000000b074        0x0 tests/slli.o
- .data          0x000000000000b074        0x0 tests/remu.o
- .bss           0x000000000000b074        0x0 tests/remu.o
- .data          0x000000000000b074        0x0 tests/ori.o
- .bss           0x000000000000b074        0x0 tests/ori.o
- .data          0x000000000000b074        0xa tests/sb.o
- .bss           0x000000000000b07e        0x0 tests/sb.o
- *fill*         0x000000000000b07e        0x2 
- .data          0x000000000000b080        0x0 tests/jal.o
- .bss           0x000000000000b080        0x0 tests/jal.o
- .data          0x000000000000b080        0x0 tests/add.o
- .bss           0x000000000000b080        0x0 tests/add.o
- .data          0x000000000000b080        0x0 tests/j.o
- .bss           0x000000000000b080        0x0 tests/j.o
- .data          0x000000000000b080        0x0 tests/andi.o
- .bss           0x000000000000b080        0x0 tests/andi.o
- .data          0x000000000000b080        0x0 tests/sra.o
- .bss           0x000000000000b080        0x0 tests/sra.o
- .data          0x000000000000b080        0x0 tests/bge.o
- .bss           0x000000000000b080        0x0 tests/bge.o
- .data          0x000000000000b080        0x0 tests/div.o
- .bss           0x000000000000b080        0x0 tests/div.o
- .data          0x000000000000b080        0x0 tests/mulh.o
- .bss           0x000000000000b080        0x0 tests/mulh.o
- .data          0x000000000000b080        0x0 tests/mulhsu.o
- .bss           0x000000000000b080        0x0 tests/mulhsu.o
- .data          0x000000000000b080        0x0 tests/srli.o
- .bss           0x000000000000b080        0x0 tests/srli.o
- .data          0x000000000000b080        0x0 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(muldi3.o)
- .bss           0x000000000000b080        0x0 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(muldi3.o)
- .data          0x000000000000b080        0x0 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(multi3.o)
- .bss           0x000000000000b080        0x0 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(multi3.o)
- .data          0x000000000000b080        0x0 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(div.o)
- .bss           0x000000000000b080        0x0 /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a(div.o)
-                0x000000000000b080                end = .
-LOAD firmware/start.o
-LOAD firmware/irq.o
-LOAD firmware/print.o
-LOAD firmware/sieve.o
-LOAD firmware/multest.o
-LOAD firmware/stats.o
-LOAD tests/xori.o
-LOAD tests/or.o
-LOAD tests/xor.o
-LOAD tests/sub.o
-LOAD tests/lb.o
-LOAD tests/lh.o
-LOAD tests/srl.o
-LOAD tests/blt.o
-LOAD tests/and.o
-LOAD tests/srai.o
-LOAD tests/beq.o
-LOAD tests/rem.o
-LOAD tests/addi.o
-LOAD tests/mul.o
-LOAD tests/divu.o
-LOAD tests/sw.o
-LOAD tests/bne.o
-LOAD tests/auipc.o
-LOAD tests/jalr.o
-LOAD tests/bgeu.o
-LOAD tests/lw.o
-LOAD tests/mulhu.o
-LOAD tests/slti.o
-LOAD tests/slt.o
-LOAD tests/lbu.o
-LOAD tests/lhu.o
-LOAD tests/sh.o
-LOAD tests/lui.o
-LOAD tests/bltu.o
-LOAD tests/sll.o
-LOAD tests/simple.o
-LOAD tests/slli.o
-LOAD tests/remu.o
-LOAD tests/ori.o
-LOAD tests/sb.o
-LOAD tests/jal.o
-LOAD tests/add.o
-LOAD tests/j.o
-LOAD tests/andi.o
-LOAD tests/sra.o
-LOAD tests/bge.o
-LOAD tests/div.o
-LOAD tests/mulh.o
-LOAD tests/mulhsu.o
-LOAD tests/srli.o
-LOAD /opt/riscv32i/lib/gcc/riscv32-unknown-elf/7.2.0/libgcc.a
-OUTPUT(firmware/firmware.elf elf32-littleriscv)
diff --git a/picorv32_firmware/firmware/multest.c b/picorv32_firmware/firmware/multest.c
index 93e48df..d156d8a 100644
--- a/picorv32_firmware/firmware/multest.c
+++ b/picorv32_firmware/firmware/multest.c
@@ -35,24 +35,24 @@ void multest(void)
 		print_hex(b, 8);
 		print_chr('\n');
 
-		uint32_t h_mul, h_mulh, h_mulhsu, h_mulhu;
+		//uint32_t h_mul, h_mulh, h_mulhsu, h_mulhu;
 		print_str("hard   ");
 
-		h_mul = hard_mul(a, b);
-		print_hex(h_mul, 8);
-		print_str("  ");
+                //h_mul = hard_mul(a, b);
+		//print_hex(h_mul, 8);
+		//print_str("  ");
 
-		h_mulh = hard_mulh(a, b);
-		print_hex(h_mulh, 8);
-		print_str("  ");
+                //h_mulh = hard_mulh(a, b);
+		//print_hex(h_mulh, 8);
+		//print_str("  ");
 
-		h_mulhsu = hard_mulhsu(a, b);
-		print_hex(h_mulhsu, 8);
-		print_str("  ");
+                //h_mulhsu = hard_mulhsu(a, b);
+		//print_hex(h_mulhsu, 8);
+		//print_str("  ");
 
-		h_mulhu = hard_mulhu(a, b);
-		print_hex(h_mulhu, 8);
-		print_chr('\n');
+                //	h_mulhu = hard_mulhu(a, b);
+		//print_hex(h_mulhu, 8);
+		//print_chr('\n');
 
 		uint32_t s_mul, s_mulh, s_mulhsu, s_mulhu;
 		print_str("soft   ");
@@ -73,11 +73,11 @@ void multest(void)
 		print_hex(s_mulhu, 8);
 		print_str("  ");
 
-		if (s_mul != h_mul || s_mulh != h_mulh || s_mulhsu != h_mulhsu || s_mulhu != h_mulhu) {
+		/*if (s_mul != h_mul || s_mulh != h_mulh || s_mulhsu != h_mulhsu || s_mulhu != h_mulhu) {
 			print_str("ERROR!\n");
 			__asm__ volatile ("ebreak");
 			return;
-		}
+                        }*/
 
 		print_str(" OK\n");
 	}
diff --git a/picorv32_firmware/firmware/multest.o b/picorv32_firmware/firmware/multest.o
deleted file mode 100644
index c219c63..0000000
Binary files a/picorv32_firmware/firmware/multest.o and /dev/null differ
diff --git a/picorv32_firmware/firmware/start.S b/picorv32_firmware/firmware/start.S
index 06d4744..82399ba 100644
--- a/picorv32_firmware/firmware/start.S
+++ b/picorv32_firmware/firmware/start.S
@@ -8,7 +8,7 @@
 #define ENABLE_QREGS
 #define ENABLE_RVTST
 #define ENABLE_SIEVE
-#define ENABLE_MULTST
+//#define ENABLE_MULTST
 #define ENABLE_STATS
 
 #ifndef ENABLE_QREGS
@@ -430,15 +430,15 @@ start:
 	TEST(or)
 	TEST(and)
 
-	TEST(mulh)
-	TEST(mulhsu)
-	TEST(mulhu)
-	TEST(mul)
+//	TEST(mulh)
+//	TEST(mulhsu)
+//	TEST(mulhu)
+//	TEST(mul)
 
-	TEST(div)
-	TEST(divu)
-	TEST(rem)
-	TEST(remu)
+//	TEST(div)
+//	TEST(divu)
+//	TEST(rem)
+//	TEST(remu)
 
 	TEST(simple)
 
@@ -489,19 +489,19 @@ start:
 /* Hard mul functions for multest.c
  **********************************/
 
-hard_mul:
-	mul a0, a0, a1
-	ret
-
-hard_mulh:
-	mulh a0, a0, a1
-	ret
-
-hard_mulhsu:
-	mulhsu a0, a0, a1
-	ret
-
-hard_mulhu:
-	mulhu a0, a0, a1
-	ret
+//hard_mul:
+//	mul a0, a0, a1
+//	ret
+//
+//hard_mulh:
+//	mulh a0, a0, a1
+//	ret
+//
+//hard_mulhsu:
+//	mulhsu a0, a0, a1
+//	ret
+//
+//hard_mulhu:
+//	mulhu a0, a0, a1
+//	ret
 
diff --git a/picorv32_firmware/firmware/start.o b/picorv32_firmware/firmware/start.o
deleted file mode 100644
index 557a6ec..0000000
Binary files a/picorv32_firmware/firmware/start.o and /dev/null differ
diff --git a/picorv32_firmware/tests/LICENSE b/picorv32_firmware/tests/LICENSE
new file mode 100644
index 0000000..48fe522
--- /dev/null
+++ b/picorv32_firmware/tests/LICENSE
@@ -0,0 +1,24 @@
+Copyright (c) 2012-2015, The Regents of the University of California (Regents).
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+3. Neither the name of the Regents nor the
+   names of its contributors may be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
diff --git a/picorv32_firmware/tests/README b/picorv32_firmware/tests/README
new file mode 100644
index 0000000..3c1a912
--- /dev/null
+++ b/picorv32_firmware/tests/README
@@ -0,0 +1 @@
+Tests from https://github.com/riscv/riscv-tests/tree/master/isa/rv32ui
diff --git a/picorv32_firmware/tests/add.S b/picorv32_firmware/tests/add.S
new file mode 100644
index 0000000..2eb330e
--- /dev/null
+++ b/picorv32_firmware/tests/add.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# add.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  add, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  add, 0x00000002, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  add, 0x0000000a, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  add, 0xffff8000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  add, 0x80000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  add, 0x7fff8000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP( 8,  add, 0x00007fff, 0x00000000, 0x00007fff );
+  TEST_RR_OP( 9,  add, 0x7fffffff, 0x7fffffff, 0x00000000 );
+  TEST_RR_OP( 10, add, 0x80007ffe, 0x7fffffff, 0x00007fff );
+
+  TEST_RR_OP( 11, add, 0x80007fff, 0x80000000, 0x00007fff );
+  TEST_RR_OP( 12, add, 0x7fff7fff, 0x7fffffff, 0xffff8000 );
+
+  TEST_RR_OP( 13, add, 0xffffffff, 0x00000000, 0xffffffff );
+  TEST_RR_OP( 14, add, 0x00000000, 0xffffffff, 0x00000001 );
+  TEST_RR_OP( 15, add, 0xfffffffe, 0xffffffff, 0xffffffff );
+
+  TEST_RR_OP( 16, add, 0x80000000, 0x00000001, 0x7fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, add, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, add, 32, 32 );
+  TEST_RR_ZEROSRC12( 37, add, 0 );
+  TEST_RR_ZERODEST( 38, add, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/add.o b/picorv32_firmware/tests/add.o
new file mode 100644
index 0000000..ccd66dd
Binary files /dev/null and b/picorv32_firmware/tests/add.o differ
diff --git a/picorv32_firmware/tests/addi.S b/picorv32_firmware/tests/addi.S
new file mode 100644
index 0000000..f7a418b
--- /dev/null
+++ b/picorv32_firmware/tests/addi.S
@@ -0,0 +1,71 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addi.S
+#-----------------------------------------------------------------------------
+#
+# Test addi instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  addi, 0x00000000, 0x00000000, 0x000 );
+  TEST_IMM_OP( 3,  addi, 0x00000002, 0x00000001, 0x001 );
+  TEST_IMM_OP( 4,  addi, 0x0000000a, 0x00000003, 0x007 );
+
+  TEST_IMM_OP( 5,  addi, 0xfffff800, 0x00000000, 0x800 );
+  TEST_IMM_OP( 6,  addi, 0x80000000, 0x80000000, 0x000 );
+  TEST_IMM_OP( 7,  addi, 0x7ffff800, 0x80000000, 0x800 );
+
+  TEST_IMM_OP( 8,  addi, 0x000007ff, 0x00000000, 0x7ff );
+  TEST_IMM_OP( 9,  addi, 0x7fffffff, 0x7fffffff, 0x000 );
+  TEST_IMM_OP( 10, addi, 0x800007fe, 0x7fffffff, 0x7ff );
+
+  TEST_IMM_OP( 11, addi, 0x800007ff, 0x80000000, 0x7ff );
+  TEST_IMM_OP( 12, addi, 0x7ffff7ff, 0x7fffffff, 0x800 );
+
+  TEST_IMM_OP( 13, addi, 0xffffffff, 0x00000000, 0xfff );
+  TEST_IMM_OP( 14, addi, 0x00000000, 0xffffffff, 0x001 );
+  TEST_IMM_OP( 15, addi, 0xfffffffe, 0xffffffff, 0xfff );
+
+  TEST_IMM_OP( 16, addi, 0x80000000, 0x7fffffff, 0x001 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 );
+  TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 );
+  TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13,  9 );
+
+  TEST_IMM_ZEROSRC1( 24, addi, 32, 32 );
+  TEST_IMM_ZERODEST( 25, addi, 33, 50 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/addi.o b/picorv32_firmware/tests/addi.o
new file mode 100644
index 0000000..c41d99d
Binary files /dev/null and b/picorv32_firmware/tests/addi.o differ
diff --git a/picorv32_firmware/tests/and.S b/picorv32_firmware/tests/and.S
new file mode 100644
index 0000000..561ae3b
--- /dev/null
+++ b/picorv32_firmware/tests/and.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# and.S
+#-----------------------------------------------------------------------------
+#
+# Test and instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 9,  0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 );
+  TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff );
+  TEST_RR_ZEROSRC12( 26, and, 0 );
+  TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/and.o b/picorv32_firmware/tests/and.o
new file mode 100644
index 0000000..3de48c4
Binary files /dev/null and b/picorv32_firmware/tests/and.o differ
diff --git a/picorv32_firmware/tests/andi.S b/picorv32_firmware/tests/andi.S
new file mode 100644
index 0000000..c2ae94d
--- /dev/null
+++ b/picorv32_firmware/tests/andi.S
@@ -0,0 +1,55 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# andi.S
+#-----------------------------------------------------------------------------
+#
+# Test andi instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
+  TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
+  TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
+  TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 7,  0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+  TEST_IMM_DEST_BYPASS( 8,  1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+  TEST_IMM_DEST_BYPASS( 9,  2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
+
+  TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+  TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+  TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
+
+  TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
+  TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/andi.o b/picorv32_firmware/tests/andi.o
new file mode 100644
index 0000000..b72885d
Binary files /dev/null and b/picorv32_firmware/tests/andi.o differ
diff --git a/picorv32_firmware/tests/auipc.S b/picorv32_firmware/tests/auipc.S
new file mode 100644
index 0000000..c67e3c9
--- /dev/null
+++ b/picorv32_firmware/tests/auipc.S
@@ -0,0 +1,39 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# auipc.S
+#-----------------------------------------------------------------------------
+#
+# Test auipc instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 10000, \
+    .align 3; \
+    lla a0, 1f + 10000; \
+    jal a1, 1f; \
+    1: sub a0, a0, a1; \
+  )
+
+  TEST_CASE(3, a0, -10000, \
+    .align 3; \
+    lla a0, 1f - 10000; \
+    jal a1, 1f; \
+    1: sub a0, a0, a1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/auipc.o b/picorv32_firmware/tests/auipc.o
new file mode 100644
index 0000000..bb91f0f
Binary files /dev/null and b/picorv32_firmware/tests/auipc.o differ
diff --git a/picorv32_firmware/tests/beq.S b/picorv32_firmware/tests/beq.S
new file mode 100644
index 0000000..c972eff
--- /dev/null
+++ b/picorv32_firmware/tests/beq.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# beq.S
+#-----------------------------------------------------------------------------
+#
+# Test beq instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, beq,  0,  0 );
+  TEST_BR2_OP_TAKEN( 3, beq,  1,  1 );
+  TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 5, beq,  0,  1 );
+  TEST_BR2_OP_NOTTAKEN( 6, beq,  1,  0 );
+  TEST_BR2_OP_NOTTAKEN( 7, beq, -1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 8, beq,  1, -1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    beq x0, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/beq.o b/picorv32_firmware/tests/beq.o
new file mode 100644
index 0000000..372102c
Binary files /dev/null and b/picorv32_firmware/tests/beq.o differ
diff --git a/picorv32_firmware/tests/bge.S b/picorv32_firmware/tests/bge.S
new file mode 100644
index 0000000..d6aea7c
--- /dev/null
+++ b/picorv32_firmware/tests/bge.S
@@ -0,0 +1,76 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bge.S
+#-----------------------------------------------------------------------------
+#
+# Test bge instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bge,  0,  0 );
+  TEST_BR2_OP_TAKEN( 3, bge,  1,  1 );
+  TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
+  TEST_BR2_OP_TAKEN( 5, bge,  1,  0 );
+  TEST_BR2_OP_TAKEN( 6, bge,  1, -1 );
+  TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
+
+  TEST_BR2_OP_NOTTAKEN(  8, bge,  0,  1 );
+  TEST_BR2_OP_NOTTAKEN(  9, bge, -1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
+  TEST_BR2_OP_NOTTAKEN( 11, bge, -2,  1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
+
+  TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 24, x1, 3, \
+    li  x1, 1; \
+    bge x1, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/bge.o b/picorv32_firmware/tests/bge.o
new file mode 100644
index 0000000..a66735a
Binary files /dev/null and b/picorv32_firmware/tests/bge.o differ
diff --git a/picorv32_firmware/tests/bgeu.S b/picorv32_firmware/tests/bgeu.S
new file mode 100644
index 0000000..114c845
--- /dev/null
+++ b/picorv32_firmware/tests/bgeu.S
@@ -0,0 +1,76 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bgeu.S
+#-----------------------------------------------------------------------------
+#
+# Test bgeu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
+  TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
+  TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
+  TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
+  TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
+  TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
+
+  TEST_BR2_OP_NOTTAKEN(  8, bgeu, 0x00000000, 0x00000001 );
+  TEST_BR2_OP_NOTTAKEN(  9, bgeu, 0xfffffffe, 0xffffffff );
+  TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
+  TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+  TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 24, x1, 3, \
+    li  x1, 1; \
+    bgeu x1, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/bgeu.o b/picorv32_firmware/tests/bgeu.o
new file mode 100644
index 0000000..ddf7a16
Binary files /dev/null and b/picorv32_firmware/tests/bgeu.o differ
diff --git a/picorv32_firmware/tests/blt.S b/picorv32_firmware/tests/blt.S
new file mode 100644
index 0000000..12e28c3
--- /dev/null
+++ b/picorv32_firmware/tests/blt.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# blt.S
+#-----------------------------------------------------------------------------
+#
+# Test blt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, blt,  0,  1 );
+  TEST_BR2_OP_TAKEN( 3, blt, -1,  1 );
+  TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 5, blt,  1,  0 );
+  TEST_BR2_OP_NOTTAKEN( 6, blt,  1, -1 );
+  TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
+  TEST_BR2_OP_NOTTAKEN( 8, blt,  1, -2 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    blt x0, x1, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/blt.o b/picorv32_firmware/tests/blt.o
new file mode 100644
index 0000000..f7df9ae
Binary files /dev/null and b/picorv32_firmware/tests/blt.o differ
diff --git a/picorv32_firmware/tests/bltu.S b/picorv32_firmware/tests/bltu.S
new file mode 100644
index 0000000..5dcfe7e
--- /dev/null
+++ b/picorv32_firmware/tests/bltu.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bltu.S
+#-----------------------------------------------------------------------------
+#
+# Test bltu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
+  TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
+  TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
+
+  TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
+  TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
+  TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
+  TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    bltu x0, x1, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/bltu.o b/picorv32_firmware/tests/bltu.o
new file mode 100644
index 0000000..28c9f61
Binary files /dev/null and b/picorv32_firmware/tests/bltu.o differ
diff --git a/picorv32_firmware/tests/bne.S b/picorv32_firmware/tests/bne.S
new file mode 100644
index 0000000..0b33753
--- /dev/null
+++ b/picorv32_firmware/tests/bne.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bne.S
+#-----------------------------------------------------------------------------
+#
+# Test bne instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bne,  0,  1 );
+  TEST_BR2_OP_TAKEN( 3, bne,  1,  0 );
+  TEST_BR2_OP_TAKEN( 4, bne, -1,  1 );
+  TEST_BR2_OP_TAKEN( 5, bne,  1, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 6, bne,  0,  0 );
+  TEST_BR2_OP_NOTTAKEN( 7, bne,  1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    bne x1, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/bne.o b/picorv32_firmware/tests/bne.o
new file mode 100644
index 0000000..cc45986
Binary files /dev/null and b/picorv32_firmware/tests/bne.o differ
diff --git a/picorv32_firmware/tests/div.S.ignore b/picorv32_firmware/tests/div.S.ignore
new file mode 100644
index 0000000..24dc9ff
--- /dev/null
+++ b/picorv32_firmware/tests/div.S.ignore
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# div.S
+#-----------------------------------------------------------------------------
+#
+# Test div instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, div,  3,  20,   6 );
+  TEST_RR_OP( 3, div, -3, -20,   6 );
+  TEST_RR_OP( 4, div, -3,  20,  -6 );
+  TEST_RR_OP( 5, div,  3, -20,  -6 );
+
+  TEST_RR_OP( 6, div, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, div, -1<<31, -1<<31, -1 );
+
+  TEST_RR_OP( 8, div, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, div, -1,      1, 0 );
+  TEST_RR_OP(10, div, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/divu.S.ignore b/picorv32_firmware/tests/divu.S.ignore
new file mode 100644
index 0000000..cd348c9
--- /dev/null
+++ b/picorv32_firmware/tests/divu.S.ignore
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divu.S
+#-----------------------------------------------------------------------------
+#
+# Test divu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divu,                   3,  20,   6 );
+  TEST_RR_OP( 3, divu,           715827879, -20,   6 );
+  TEST_RR_OP( 4, divu,                   0,  20,  -6 );
+  TEST_RR_OP( 5, divu,                   0, -20,  -6 );
+
+  TEST_RR_OP( 6, divu, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, divu,     0,  -1<<31, -1 );
+
+  TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, divu, -1,      1, 0 );
+  TEST_RR_OP(10, divu, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/j.S b/picorv32_firmware/tests/j.S
new file mode 100644
index 0000000..259a236
--- /dev/null
+++ b/picorv32_firmware/tests/j.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# j.S
+#-----------------------------------------------------------------------------
+#
+# Test j instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test basic
+  #-------------------------------------------------------------
+
+  li  TESTNUM, 2;
+  j test_2;
+  j fail;
+test_2:
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 3, x1, 3, \
+    li  x1, 1; \
+    j 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/j.o b/picorv32_firmware/tests/j.o
new file mode 100644
index 0000000..28de446
Binary files /dev/null and b/picorv32_firmware/tests/j.o differ
diff --git a/picorv32_firmware/tests/jal.S b/picorv32_firmware/tests/jal.S
new file mode 100644
index 0000000..742abac
--- /dev/null
+++ b/picorv32_firmware/tests/jal.S
@@ -0,0 +1,60 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# jal.S
+#-----------------------------------------------------------------------------
+#
+# Test jal instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li  TESTNUM, 2
+  li  ra, 0
+
+linkaddr_2:
+  jal target_2
+  nop
+  nop
+
+  j fail
+
+target_2:
+  la  x2, linkaddr_2
+  addi x2, x2, 4
+  bne x2, ra, fail
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 3, x2, 3, \
+    li  x2, 1; \
+    jal 1f; \
+    addi x2, x2, 1; \
+    addi x2, x2, 1; \
+    addi x2, x2, 1; \
+    addi x2, x2, 1; \
+1:  addi x2, x2, 1; \
+    addi x2, x2, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/jal.o b/picorv32_firmware/tests/jal.o
new file mode 100644
index 0000000..7e511c2
Binary files /dev/null and b/picorv32_firmware/tests/jal.o differ
diff --git a/picorv32_firmware/tests/jalr.S b/picorv32_firmware/tests/jalr.S
new file mode 100644
index 0000000..ebe3731
--- /dev/null
+++ b/picorv32_firmware/tests/jalr.S
@@ -0,0 +1,88 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# jalr.S
+#-----------------------------------------------------------------------------
+#
+# Test jalr instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li  TESTNUM, 2
+  li  x31, 0
+  la  x2, target_2
+
+linkaddr_2:
+  jalr x19, x2, 0
+  nop
+  nop
+
+  j fail
+
+target_2:
+  la  x1, linkaddr_2
+  addi x1, x1, 4
+  bne x1, x19, fail
+
+  #-------------------------------------------------------------
+  # Test 3: Check r0 target and that r31 is not modified
+  #-------------------------------------------------------------
+
+test_3:
+  li  TESTNUM, 3
+  li  x31, 0
+  la  x3, target_3
+
+linkaddr_3:
+  jalr x0, x3, 0
+  nop
+
+  j fail
+
+target_3:
+  bne x31, x0, fail
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
+  TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
+  TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 7, x1, 4, \
+    li  x1, 1; \
+    la  x2, 1f;
+    jalr x19, x2, -4; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/jalr.o b/picorv32_firmware/tests/jalr.o
new file mode 100644
index 0000000..5dc4ed4
Binary files /dev/null and b/picorv32_firmware/tests/jalr.o differ
diff --git a/picorv32_firmware/tests/lb.S b/picorv32_firmware/tests/lb.S
new file mode 100644
index 0000000..eaf7902
--- /dev/null
+++ b/picorv32_firmware/tests/lb.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lb.S
+#-----------------------------------------------------------------------------
+#
+# Test lb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lb, 0xffffffff, 0,  tdat );
+  TEST_LD_OP( 3, lb, 0x00000000, 1,  tdat );
+  TEST_LD_OP( 4, lb, 0xfffffff0, 2,  tdat );
+  TEST_LD_OP( 5, lb, 0x0000000f, 3, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lb, 0xffffffff, -3, tdat4 );
+  TEST_LD_OP( 7, lb, 0x00000000, -2,  tdat4 );
+  TEST_LD_OP( 8, lb, 0xfffffff0, -1,  tdat4 );
+  TEST_LD_OP( 9, lb, 0x0000000f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0xffffffff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lb x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x00000000, \
+    la  x1, tdat; \
+    addi x1, x1, -6; \
+    lb x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffff0, 1, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lb, 0x0000000f, 1, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lb, 0x00000000, 1, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffff0, 1, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x0000000f, 1, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x00000000, 1, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lb  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lb  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .byte 0xff
+tdat2:  .byte 0x00
+tdat3:  .byte 0xf0
+tdat4:  .byte 0x0f
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/lb.o b/picorv32_firmware/tests/lb.o
new file mode 100644
index 0000000..bd1173a
Binary files /dev/null and b/picorv32_firmware/tests/lb.o differ
diff --git a/picorv32_firmware/tests/lbu.S b/picorv32_firmware/tests/lbu.S
new file mode 100644
index 0000000..027b643
--- /dev/null
+++ b/picorv32_firmware/tests/lbu.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lbu.S
+#-----------------------------------------------------------------------------
+#
+# Test lbu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lbu, 0x000000ff, 0,  tdat );
+  TEST_LD_OP( 3, lbu, 0x00000000, 1,  tdat );
+  TEST_LD_OP( 4, lbu, 0x000000f0, 2,  tdat );
+  TEST_LD_OP( 5, lbu, 0x0000000f, 3, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lbu, 0x000000ff, -3, tdat4 );
+  TEST_LD_OP( 7, lbu, 0x00000000, -2,  tdat4 );
+  TEST_LD_OP( 8, lbu, 0x000000f0, -1,  tdat4 );
+  TEST_LD_OP( 9, lbu, 0x0000000f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x000000ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lbu x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x00000000, \
+    la  x1, tdat; \
+    addi x1, x1, -6; \
+    lbu x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x000000f0, 1, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x0000000f, 1, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x00000000, 1, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x000000f0, 1, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x0000000f, 1, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x00000000, 1, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lbu  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lbu  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .byte 0xff
+tdat2:  .byte 0x00
+tdat3:  .byte 0xf0
+tdat4:  .byte 0x0f
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/lbu.o b/picorv32_firmware/tests/lbu.o
new file mode 100644
index 0000000..2fefcd1
Binary files /dev/null and b/picorv32_firmware/tests/lbu.o differ
diff --git a/picorv32_firmware/tests/lh.S b/picorv32_firmware/tests/lh.S
new file mode 100644
index 0000000..d8eda91
--- /dev/null
+++ b/picorv32_firmware/tests/lh.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lh.S
+#-----------------------------------------------------------------------------
+#
+# Test lh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lh, 0x000000ff, 0,  tdat );
+  TEST_LD_OP( 3, lh, 0xffffff00, 2,  tdat );
+  TEST_LD_OP( 4, lh, 0x00000ff0, 4,  tdat );
+  TEST_LD_OP( 5, lh, 0xfffff00f, 6, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lh, 0x000000ff, -6,  tdat4 );
+  TEST_LD_OP( 7, lh, 0xffffff00, -4,  tdat4 );
+  TEST_LD_OP( 8, lh, 0x00000ff0, -2,  tdat4 );
+  TEST_LD_OP( 9, lh, 0xfffff00f,  0, tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x000000ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lh x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0xffffff00, \
+    la  x1, tdat; \
+    addi x1, x1, -5; \
+    lh x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lh, 0x00000ff0, 2, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffff00f, 2, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffff00, 2, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x00000ff0, 2, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffff00f, 2, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffff00, 2, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lh  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lh  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .half 0x00ff
+tdat2:  .half 0xff00
+tdat3:  .half 0x0ff0
+tdat4:  .half 0xf00f
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/lh.o b/picorv32_firmware/tests/lh.o
new file mode 100644
index 0000000..e4c99bd
Binary files /dev/null and b/picorv32_firmware/tests/lh.o differ
diff --git a/picorv32_firmware/tests/lhu.S b/picorv32_firmware/tests/lhu.S
new file mode 100644
index 0000000..71daec6
--- /dev/null
+++ b/picorv32_firmware/tests/lhu.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lhu.S
+#-----------------------------------------------------------------------------
+#
+# Test lhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lhu, 0x000000ff, 0,  tdat );
+  TEST_LD_OP( 3, lhu, 0x0000ff00, 2,  tdat );
+  TEST_LD_OP( 4, lhu, 0x00000ff0, 4,  tdat );
+  TEST_LD_OP( 5, lhu, 0x0000f00f, 6, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lhu, 0x000000ff, -6,  tdat4 );
+  TEST_LD_OP( 7, lhu, 0x0000ff00, -4,  tdat4 );
+  TEST_LD_OP( 8, lhu, 0x00000ff0, -2,  tdat4 );
+  TEST_LD_OP( 9, lhu, 0x0000f00f,  0, tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x000000ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lhu x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x0000ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -5; \
+    lhu x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x00000ff0, 2, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x0000f00f, 2, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x0000ff00, 2, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x00000ff0, 2, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x0000f00f, 2, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x0000ff00, 2, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lhu  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lhu  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .half 0x00ff
+tdat2:  .half 0xff00
+tdat3:  .half 0x0ff0
+tdat4:  .half 0xf00f
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/lhu.o b/picorv32_firmware/tests/lhu.o
new file mode 100644
index 0000000..9e7f099
Binary files /dev/null and b/picorv32_firmware/tests/lhu.o differ
diff --git a/picorv32_firmware/tests/lui.S b/picorv32_firmware/tests/lui.S
new file mode 100644
index 0000000..50822d1
--- /dev/null
+++ b/picorv32_firmware/tests/lui.S
@@ -0,0 +1,36 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lui.S
+#-----------------------------------------------------------------------------
+#
+# Test lui instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_CASE( 2, x1, 0x00000000, lui x1, 0x00000 );
+  TEST_CASE( 3, x1, 0xfffff800, lui x1, 0xfffff;sra x1,x1,1);
+  TEST_CASE( 4, x1, 0x000007ff, lui x1, 0x7ffff;sra x1,x1,20);
+  TEST_CASE( 5, x1, 0xfffff800, lui x1, 0x80000;sra x1,x1,20);
+
+  TEST_CASE( 6, x0, 0, lui x0, 0x80000 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/lui.o b/picorv32_firmware/tests/lui.o
new file mode 100644
index 0000000..3a35aa5
Binary files /dev/null and b/picorv32_firmware/tests/lui.o differ
diff --git a/picorv32_firmware/tests/lw.S b/picorv32_firmware/tests/lw.S
new file mode 100644
index 0000000..4a07838
--- /dev/null
+++ b/picorv32_firmware/tests/lw.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lw.S
+#-----------------------------------------------------------------------------
+#
+# Test lw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lw, 0x00ff00ff, 0,  tdat );
+  TEST_LD_OP( 3, lw, 0xff00ff00, 4,  tdat );
+  TEST_LD_OP( 4, lw, 0x0ff00ff0, 8,  tdat );
+  TEST_LD_OP( 5, lw, 0xf00ff00f, 12, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lw, 0x00ff00ff, -12, tdat4 );
+  TEST_LD_OP( 7, lw, 0xff00ff00, -8,  tdat4 );
+  TEST_LD_OP( 8, lw, 0x0ff00ff0, -4,  tdat4 );
+  TEST_LD_OP( 9, lw, 0xf00ff00f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x00ff00ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lw x3, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0xff00ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -3; \
+    lw x3, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lw, 0x0ff00ff0, 4, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lw, 0xf00ff00f, 4, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lw, 0xff00ff00, 4, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x0ff00ff0, 4, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xf00ff00f, 4, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xff00ff00, 4, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x3, tdat; \
+    lw  x2, 0(x3); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x3, tdat; \
+    lw  x2, 0(x3); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .word 0x00ff00ff
+tdat2:  .word 0xff00ff00
+tdat3:  .word 0x0ff00ff0
+tdat4:  .word 0xf00ff00f
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/lw.o b/picorv32_firmware/tests/lw.o
new file mode 100644
index 0000000..1b6a9ad
Binary files /dev/null and b/picorv32_firmware/tests/lw.o differ
diff --git a/picorv32_firmware/tests/mul.S.ignore b/picorv32_firmware/tests/mul.S.ignore
new file mode 100644
index 0000000..0368629
--- /dev/null
+++ b/picorv32_firmware/tests/mul.S.ignore
@@ -0,0 +1,84 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mul.S
+#-----------------------------------------------------------------------------
+#
+# Test mul instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP(32,  mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
+  TEST_RR_OP(33,  mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
+
+  TEST_RR_OP( 2,  mul, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mul, 0x00000001, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mul, 0x00000015, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mul, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mul, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mul, 0x00000000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP(30,  mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(34,  mul, 0x00000000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(35,  mul, 0x00000001, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(36,  mul, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(37,  mul, 0xffffffff, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
+  TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
+  TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
+  TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
+  TEST_RR_ZEROSRC12( 28, mul, 0 );
+  TEST_RR_ZERODEST( 29, mul, 33, 34 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/mulh.S.ignore b/picorv32_firmware/tests/mulh.S.ignore
new file mode 100644
index 0000000..e583f5f
--- /dev/null
+++ b/picorv32_firmware/tests/mulh.S.ignore
@@ -0,0 +1,81 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulh.S
+#-----------------------------------------------------------------------------
+#
+# Test mulh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulh, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulh, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulh, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulh, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulh, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulh, 0x00000000, 0x80000000, 0x00000000 );
+
+  TEST_RR_OP(30,  mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(32,  mulh, 0x00010000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(33,  mulh, 0x00000000, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(34,  mulh, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(35,  mulh, 0xffffffff, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
+  TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
+  TEST_RR_ZEROSRC12( 28, mulh, 0 );
+  TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/mulhsu.S.ignore b/picorv32_firmware/tests/mulhsu.S.ignore
new file mode 100644
index 0000000..28b3690
--- /dev/null
+++ b/picorv32_firmware/tests/mulhsu.S.ignore
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhsu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhsu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhsu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhsu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhsu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulhsu, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP(30,  mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(32,  mulhsu, 0xff010000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(33,  mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(34,  mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(35,  mulhsu, 0x00000000, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
+  TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
+  TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
+  TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
+
+
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/mulhu.S.ignore b/picorv32_firmware/tests/mulhu.S.ignore
new file mode 100644
index 0000000..601dcff
--- /dev/null
+++ b/picorv32_firmware/tests/mulhu.S.ignore
@@ -0,0 +1,82 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhu, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulhu, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP(30,  mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(32,  mulhu, 0xfe010000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(33,  mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(34,  mulhu, 0x00000000, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(35,  mulhu, 0x00000000, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
+  TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
+  TEST_RR_ZEROSRC12( 28, mulhu, 0 );
+  TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
+
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/or.S b/picorv32_firmware/tests/or.S
new file mode 100644
index 0000000..110bcc4
--- /dev/null
+++ b/picorv32_firmware/tests/or.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# or.S
+#-----------------------------------------------------------------------------
+#
+# Test or instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 9,  0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 );
+  TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff );
+  TEST_RR_ZEROSRC12( 26, or, 0 );
+  TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/or.o b/picorv32_firmware/tests/or.o
new file mode 100644
index 0000000..16d1f10
Binary files /dev/null and b/picorv32_firmware/tests/or.o differ
diff --git a/picorv32_firmware/tests/ori.S b/picorv32_firmware/tests/ori.S
new file mode 100644
index 0000000..a674784
--- /dev/null
+++ b/picorv32_firmware/tests/ori.S
@@ -0,0 +1,55 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ori.S
+#-----------------------------------------------------------------------------
+#
+# Test ori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2, ori, 0xffffff0f, 0xff00ff00, 0xf0f );
+  TEST_IMM_OP( 3, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
+  TEST_IMM_OP( 4, ori, 0x00ff07ff, 0x00ff00ff, 0x70f );
+  TEST_IMM_OP( 5, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 7,  0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
+  TEST_IMM_DEST_BYPASS( 8,  1, ori, 0x00ff07ff, 0x00ff00ff, 0x70f );
+  TEST_IMM_DEST_BYPASS( 9,  2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+  TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x0ff00ff0, 0x0ff00ff0, 0x0f0 );
+  TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffff, 0x00ff00ff, 0xf0f );
+  TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+  TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
+  TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/ori.o b/picorv32_firmware/tests/ori.o
new file mode 100644
index 0000000..ef13d27
Binary files /dev/null and b/picorv32_firmware/tests/ori.o differ
diff --git a/picorv32_firmware/tests/rem.S.ignore b/picorv32_firmware/tests/rem.S.ignore
new file mode 100644
index 0000000..7955736
--- /dev/null
+++ b/picorv32_firmware/tests/rem.S.ignore
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# rem.S
+#-----------------------------------------------------------------------------
+#
+# Test rem instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, rem,  2,  20,   6 );
+  TEST_RR_OP( 3, rem, -2, -20,   6 );
+  TEST_RR_OP( 4, rem,  2,  20,  -6 );
+  TEST_RR_OP( 5, rem, -2, -20,  -6 );
+
+  TEST_RR_OP( 6, rem,  0, -1<<31,  1 );
+  TEST_RR_OP( 7, rem,  0, -1<<31, -1 );
+
+  TEST_RR_OP( 8, rem, -1<<31, -1<<31, 0 );
+  TEST_RR_OP( 9, rem,      1,      1, 0 );
+  TEST_RR_OP(10, rem,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/remu.S.ignore b/picorv32_firmware/tests/remu.S.ignore
new file mode 100644
index 0000000..a96cfc1
--- /dev/null
+++ b/picorv32_firmware/tests/remu.S.ignore
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remu.S
+#-----------------------------------------------------------------------------
+#
+# Test remu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, remu,   2,  20,   6 );
+  TEST_RR_OP( 3, remu,   2, -20,   6 );
+  TEST_RR_OP( 4, remu,  20,  20,  -6 );
+  TEST_RR_OP( 5, remu, -20, -20,  -6 );
+
+  TEST_RR_OP( 6, remu,      0, -1<<31,  1 );
+  TEST_RR_OP( 7, remu, -1<<31, -1<<31, -1 );
+
+  TEST_RR_OP( 8, remu, -1<<31, -1<<31, 0 );
+  TEST_RR_OP( 9, remu,      1,      1, 0 );
+  TEST_RR_OP(10, remu,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/riscv_test.h b/picorv32_firmware/tests/riscv_test.h
new file mode 100644
index 0000000..71a4366
--- /dev/null
+++ b/picorv32_firmware/tests/riscv_test.h
@@ -0,0 +1,64 @@
+#ifndef _ENV_PICORV32_TEST_H
+#define _ENV_PICORV32_TEST_H
+
+#ifndef TEST_FUNC_NAME
+#  define TEST_FUNC_NAME mytest
+#  define TEST_FUNC_TXT "mytest"
+#  define TEST_FUNC_RET mytest_ret
+#endif
+
+#define RVTEST_RV32U
+#define TESTNUM x28
+
+#define RVTEST_CODE_BEGIN		\
+	.text;				\
+	.global TEST_FUNC_NAME;		\
+	.global TEST_FUNC_RET;		\
+TEST_FUNC_NAME:				\
+	lui	a0,%hi(.test_name);	\
+	addi	a0,a0,%lo(.test_name);	\
+	lui	a2,0x10000000>>12;	\
+.prname_next:				\
+	lb	a1,0(a0);		\
+	beq	a1,zero,.prname_done;	\
+	sw	a1,0(a2);		\
+	addi	a0,a0,1;		\
+	jal	zero,.prname_next;	\
+.test_name:				\
+	.ascii TEST_FUNC_TXT;		\
+	.byte 0x00;			\
+	.balign 4, 0;			\
+.prname_done:				\
+	addi	a1,zero,'.';		\
+	sw	a1,0(a2);		\
+	sw	a1,0(a2);
+
+#define RVTEST_PASS			\
+	lui	a0,0x10000000>>12;	\
+	addi	a1,zero,'O';		\
+	addi	a2,zero,'K';		\
+	addi	a3,zero,'\n';		\
+	sw	a1,0(a0);		\
+	sw	a2,0(a0);		\
+	sw	a3,0(a0);		\
+	jal	zero,TEST_FUNC_RET;
+
+#define RVTEST_FAIL			\
+	lui	a0,0x10000000>>12;	\
+	addi	a1,zero,'E';		\
+	addi	a2,zero,'R';		\
+	addi	a3,zero,'O';		\
+	addi	a4,zero,'\n';		\
+	sw	a1,0(a0);		\
+	sw	a2,0(a0);		\
+	sw	a2,0(a0);		\
+	sw	a3,0(a0);		\
+	sw	a2,0(a0);		\
+	sw	a4,0(a0);		\
+	ebreak;
+
+#define RVTEST_CODE_END
+#define RVTEST_DATA_BEGIN .balign 4;
+#define RVTEST_DATA_END
+
+#endif
diff --git a/picorv32_firmware/tests/sb.S b/picorv32_firmware/tests/sb.S
new file mode 100644
index 0000000..05d1894
--- /dev/null
+++ b/picorv32_firmware/tests/sb.S
@@ -0,0 +1,96 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sb.S
+#-----------------------------------------------------------------------------
+#
+# Test sb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, lb, sb, 0xffffffaa, 0, tdat );
+  TEST_ST_OP( 3, lb, sb, 0x00000000, 1, tdat );
+  TEST_ST_OP( 4, lh, sb, 0xffffefa0, 2, tdat );
+  TEST_ST_OP( 5, lb, sb, 0x0000000a, 3, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, lb, sb, 0xffffffaa, -3, tdat8 );
+  TEST_ST_OP( 7, lb, sb, 0x00000000, -2, tdat8 );
+  TEST_ST_OP( 8, lb, sb, 0xffffffa0, -1, tdat8 );
+  TEST_ST_OP( 9, lb, sb, 0x0000000a, 0,  tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x78, \
+    la  x1, tdat9; \
+    li  x2, 0x12345678; \
+    addi x4, x1, -32; \
+    sb x2, 32(x4); \
+    lb x3, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0xffffff98, \
+    la  x1, tdat9; \
+    li  x2, 0x00003098; \
+    addi x1, x1, -6; \
+    sb x2, 7(x1); \
+    la  x4, tdat10; \
+    lb x3, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffdd, 0, tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffcd, 1, tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffcc, 2, tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffbc, 3, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffbb, 4, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffab, 5, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat );
+
+  li a0, 0xef
+  la a1, tdat
+  sb a0, 3(a1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .byte 0xef
+tdat2:  .byte 0xef
+tdat3:  .byte 0xef
+tdat4:  .byte 0xef
+tdat5:  .byte 0xef
+tdat6:  .byte 0xef
+tdat7:  .byte 0xef
+tdat8:  .byte 0xef
+tdat9:  .byte 0xef
+tdat10: .byte 0xef
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/sb.o b/picorv32_firmware/tests/sb.o
new file mode 100644
index 0000000..fe1fa93
Binary files /dev/null and b/picorv32_firmware/tests/sb.o differ
diff --git a/picorv32_firmware/tests/sh.S b/picorv32_firmware/tests/sh.S
new file mode 100644
index 0000000..387e181
--- /dev/null
+++ b/picorv32_firmware/tests/sh.S
@@ -0,0 +1,96 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh.S
+#-----------------------------------------------------------------------------
+#
+# Test sh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, lh, sh, 0x000000aa, 0, tdat );
+  TEST_ST_OP( 3, lh, sh, 0xffffaa00, 2, tdat );
+  TEST_ST_OP( 4, lw, sh, 0xbeef0aa0, 4, tdat );
+  TEST_ST_OP( 5, lh, sh, 0xffffa00a, 6, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, lh, sh, 0x000000aa, -6, tdat8 );
+  TEST_ST_OP( 7, lh, sh, 0xffffaa00, -4, tdat8 );
+  TEST_ST_OP( 8, lh, sh, 0x00000aa0, -2, tdat8 );
+  TEST_ST_OP( 9, lh, sh, 0xffffa00a, 0,  tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x5678, \
+    la  x1, tdat9; \
+    li  x2, 0x12345678; \
+    addi x4, x1, -32; \
+    sh x2, 32(x4); \
+    lh x3, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x3098, \
+    la  x1, tdat9; \
+    li  x2, 0x00003098; \
+    addi x1, x1, -5; \
+    sh x2, 7(x1); \
+    la  x4, tdat10; \
+    lh x3, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffccdd, 0,  tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffbccd, 2,  tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffbbcc, 4,  tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffabbc, 6, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffaabb, 8, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffdaab, 10, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0,  tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2,  tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4,  tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
+
+  li a0, 0xbeef
+  la a1, tdat
+  sh a0, 6(a1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .half 0xbeef
+tdat2:  .half 0xbeef
+tdat3:  .half 0xbeef
+tdat4:  .half 0xbeef
+tdat5:  .half 0xbeef
+tdat6:  .half 0xbeef
+tdat7:  .half 0xbeef
+tdat8:  .half 0xbeef
+tdat9:  .half 0xbeef
+tdat10: .half 0xbeef
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/sh.o b/picorv32_firmware/tests/sh.o
new file mode 100644
index 0000000..d2b573a
Binary files /dev/null and b/picorv32_firmware/tests/sh.o differ
diff --git a/picorv32_firmware/tests/simple.S b/picorv32_firmware/tests/simple.S
new file mode 100644
index 0000000..92cf203
--- /dev/null
+++ b/picorv32_firmware/tests/simple.S
@@ -0,0 +1,27 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# simple.S
+#-----------------------------------------------------------------------------
+#
+# This is the most basic self checking test. If your simulator does not
+# pass thiss then there is little chance that it will pass any of the
+# more complicated self checking tests.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+RVTEST_PASS
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/simple.o b/picorv32_firmware/tests/simple.o
new file mode 100644
index 0000000..0c91173
Binary files /dev/null and b/picorv32_firmware/tests/simple.o differ
diff --git a/picorv32_firmware/tests/sll.S b/picorv32_firmware/tests/sll.S
new file mode 100644
index 0000000..d297ac5
--- /dev/null
+++ b/picorv32_firmware/tests/sll.S
@@ -0,0 +1,90 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sll.S
+#-----------------------------------------------------------------------------
+#
+# Test sll instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sll, 0x00000001, 0x00000001, 0  );
+  TEST_RR_OP( 3,  sll, 0x00000002, 0x00000001, 1  );
+  TEST_RR_OP( 4,  sll, 0x00000080, 0x00000001, 7  );
+  TEST_RR_OP( 5,  sll, 0x00004000, 0x00000001, 14 );
+  TEST_RR_OP( 6,  sll, 0x80000000, 0x00000001, 31 );
+
+  TEST_RR_OP( 7,  sll, 0xffffffff, 0xffffffff, 0  );
+  TEST_RR_OP( 8,  sll, 0xfffffffe, 0xffffffff, 1  );
+  TEST_RR_OP( 9,  sll, 0xffffff80, 0xffffffff, 7  );
+  TEST_RR_OP( 10, sll, 0xffffc000, 0xffffffff, 14 );
+  TEST_RR_OP( 11, sll, 0x80000000, 0xffffffff, 31 );
+
+  TEST_RR_OP( 12, sll, 0x21212121, 0x21212121, 0  );
+  TEST_RR_OP( 13, sll, 0x42424242, 0x21212121, 1  );
+  TEST_RR_OP( 14, sll, 0x90909080, 0x21212121, 7  );
+  TEST_RR_OP( 15, sll, 0x48484000, 0x21212121, 14 );
+  TEST_RR_OP( 16, sll, 0x80000000, 0x21212121, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, sll, 0x21212121, 0x21212121, 0xffffffe0 );
+  TEST_RR_OP( 18, sll, 0x42424242, 0x21212121, 0xffffffe1 );
+  TEST_RR_OP( 19, sll, 0x90909080, 0x21212121, 0xffffffe7 );
+  TEST_RR_OP( 20, sll, 0x48484000, 0x21212121, 0xffffffee );
+  TEST_RR_OP( 21, sll, 0x00000000, 0x21212120, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sll, 0x00000080, 0x00000001, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sll, 0x00004000, 0x00000001, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sll, 0x80000000, 0x00000001, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x00000080, 0x00000001, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x00004000, 0x00000001, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x80000000, 0x00000001, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x00000080, 0x00000001, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x00004000, 0x00000001, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x80000000, 0x00000001, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x00000080, 0x00000001, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x00004000, 0x00000001, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x80000000, 0x00000001, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x00000080, 0x00000001, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x00004000, 0x00000001, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x80000000, 0x00000001, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sll, 0 );
+  TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/sll.o b/picorv32_firmware/tests/sll.o
new file mode 100644
index 0000000..5c94567
Binary files /dev/null and b/picorv32_firmware/tests/sll.o differ
diff --git a/picorv32_firmware/tests/slli.S b/picorv32_firmware/tests/slli.S
new file mode 100644
index 0000000..a51eec9
--- /dev/null
+++ b/picorv32_firmware/tests/slli.S
@@ -0,0 +1,68 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slli.S
+#-----------------------------------------------------------------------------
+#
+# Test slli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  slli, 0x00000001, 0x00000001, 0  );
+  TEST_IMM_OP( 3,  slli, 0x00000002, 0x00000001, 1  );
+  TEST_IMM_OP( 4,  slli, 0x00000080, 0x00000001, 7  );
+  TEST_IMM_OP( 5,  slli, 0x00004000, 0x00000001, 14 );
+  TEST_IMM_OP( 6,  slli, 0x80000000, 0x00000001, 31 );
+
+  TEST_IMM_OP( 7,  slli, 0xffffffff, 0xffffffff, 0  );
+  TEST_IMM_OP( 8,  slli, 0xfffffffe, 0xffffffff, 1  );
+  TEST_IMM_OP( 9,  slli, 0xffffff80, 0xffffffff, 7  );
+  TEST_IMM_OP( 10, slli, 0xffffc000, 0xffffffff, 14 );
+  TEST_IMM_OP( 11, slli, 0x80000000, 0xffffffff, 31 );
+
+  TEST_IMM_OP( 12, slli, 0x21212121, 0x21212121, 0  );
+  TEST_IMM_OP( 13, slli, 0x42424242, 0x21212121, 1  );
+  TEST_IMM_OP( 14, slli, 0x90909080, 0x21212121, 7  );
+  TEST_IMM_OP( 15, slli, 0x48484000, 0x21212121, 14 );
+  TEST_IMM_OP( 16, slli, 0x80000000, 0x21212121, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x00000080, 0x00000001, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x00004000, 0x00000001, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x80000000, 0x00000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x00000080, 0x00000001, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x00004000, 0x00000001, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x80000000, 0x00000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, slli, 0, 31 );
+  TEST_IMM_ZERODEST( 25, slli, 33, 20 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/slli.o b/picorv32_firmware/tests/slli.o
new file mode 100644
index 0000000..7a13bdb
Binary files /dev/null and b/picorv32_firmware/tests/slli.o differ
diff --git a/picorv32_firmware/tests/slt.S b/picorv32_firmware/tests/slt.S
new file mode 100644
index 0000000..3abf82b
--- /dev/null
+++ b/picorv32_firmware/tests/slt.S
@@ -0,0 +1,84 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slt.S
+#-----------------------------------------------------------------------------
+#
+# Test slt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  slt, 0, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  slt, 0, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  slt, 1, 0x00000003, 0x00000007 );
+  TEST_RR_OP( 5,  slt, 0, 0x00000007, 0x00000003 );
+
+  TEST_RR_OP( 6,  slt, 0, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 7,  slt, 1, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 8,  slt, 1, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP( 9,  slt, 1, 0x00000000, 0x00007fff );
+  TEST_RR_OP( 10, slt, 0, 0x7fffffff, 0x00000000 );
+  TEST_RR_OP( 11, slt, 0, 0x7fffffff, 0x00007fff );
+
+  TEST_RR_OP( 12, slt, 1, 0x80000000, 0x00007fff );
+  TEST_RR_OP( 13, slt, 0, 0x7fffffff, 0xffff8000 );
+
+  TEST_RR_OP( 14, slt, 0, 0x00000000, 0xffffffff );
+  TEST_RR_OP( 15, slt, 1, 0xffffffff, 0x00000001 );
+  TEST_RR_OP( 16, slt, 0, 0xffffffff, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 );
+  TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 );
+  TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 );
+  TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 );
+  TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1,  9, 13 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1,  8, 13 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1,  7, 13 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1,  6, 13 );
+
+  TEST_RR_ZEROSRC1( 35, slt, 0, -1 );
+  TEST_RR_ZEROSRC2( 36, slt, 1, -1 );
+  TEST_RR_ZEROSRC12( 37, slt, 0 );
+  TEST_RR_ZERODEST( 38, slt, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/slt.o b/picorv32_firmware/tests/slt.o
new file mode 100644
index 0000000..50cc037
Binary files /dev/null and b/picorv32_firmware/tests/slt.o differ
diff --git a/picorv32_firmware/tests/slti.S b/picorv32_firmware/tests/slti.S
new file mode 100644
index 0000000..730cbe2
--- /dev/null
+++ b/picorv32_firmware/tests/slti.S
@@ -0,0 +1,70 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slti.S
+#-----------------------------------------------------------------------------
+#
+# Test slti instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  slti, 0, 0x00000000, 0x000 );
+  TEST_IMM_OP( 3,  slti, 0, 0x00000001, 0x001 );
+  TEST_IMM_OP( 4,  slti, 1, 0x00000003, 0x007 );
+  TEST_IMM_OP( 5,  slti, 0, 0x00000007, 0x003 );
+
+  TEST_IMM_OP( 6,  slti, 0, 0x00000000, 0x800 );
+  TEST_IMM_OP( 7,  slti, 1, 0x80000000, 0x000 );
+  TEST_IMM_OP( 8,  slti, 1, 0x80000000, 0x800 );
+
+  TEST_IMM_OP( 9,  slti, 1, 0x00000000, 0x7ff );
+  TEST_IMM_OP( 10, slti, 0, 0x7fffffff, 0x000 );
+  TEST_IMM_OP( 11, slti, 0, 0x7fffffff, 0x7ff );
+
+  TEST_IMM_OP( 12, slti, 1, 0x80000000, 0x7ff );
+  TEST_IMM_OP( 13, slti, 0, 0x7fffffff, 0x800 );
+
+  TEST_IMM_OP( 14, slti, 0, 0x00000000, 0xfff );
+  TEST_IMM_OP( 15, slti, 1, 0xffffffff, 0x001 );
+  TEST_IMM_OP( 16, slti, 0, 0xffffffff, 0xfff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
+  TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
+  TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17,  8 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
+
+  TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
+  TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/slti.o b/picorv32_firmware/tests/slti.o
new file mode 100644
index 0000000..f7449ab
Binary files /dev/null and b/picorv32_firmware/tests/slti.o differ
diff --git a/picorv32_firmware/tests/sra.S b/picorv32_firmware/tests/sra.S
new file mode 100644
index 0000000..8c1de36
--- /dev/null
+++ b/picorv32_firmware/tests/sra.S
@@ -0,0 +1,90 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sra.S
+#-----------------------------------------------------------------------------
+#
+# Test sra instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sra, 0x80000000, 0x80000000, 0  );
+  TEST_RR_OP( 3,  sra, 0xc0000000, 0x80000000, 1  );
+  TEST_RR_OP( 4,  sra, 0xff000000, 0x80000000, 7  );
+  TEST_RR_OP( 5,  sra, 0xfffe0000, 0x80000000, 14 );
+  TEST_RR_OP( 6,  sra, 0xffffffff, 0x80000001, 31 );
+
+  TEST_RR_OP( 7,  sra, 0x7fffffff, 0x7fffffff, 0  );
+  TEST_RR_OP( 8,  sra, 0x3fffffff, 0x7fffffff, 1  );
+  TEST_RR_OP( 9,  sra, 0x00ffffff, 0x7fffffff, 7  );
+  TEST_RR_OP( 10, sra, 0x0001ffff, 0x7fffffff, 14 );
+  TEST_RR_OP( 11, sra, 0x00000000, 0x7fffffff, 31 );
+
+  TEST_RR_OP( 12, sra, 0x81818181, 0x81818181, 0  );
+  TEST_RR_OP( 13, sra, 0xc0c0c0c0, 0x81818181, 1  );
+  TEST_RR_OP( 14, sra, 0xff030303, 0x81818181, 7  );
+  TEST_RR_OP( 15, sra, 0xfffe0606, 0x81818181, 14 );
+  TEST_RR_OP( 16, sra, 0xffffffff, 0x81818181, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, sra, 0x81818181, 0x81818181, 0xffffffc0 );
+  TEST_RR_OP( 18, sra, 0xc0c0c0c0, 0x81818181, 0xffffffc1 );
+  TEST_RR_OP( 19, sra, 0xff030303, 0x81818181, 0xffffffc7 );
+  TEST_RR_OP( 20, sra, 0xfffe0606, 0x81818181, 0xffffffce );
+  TEST_RR_OP( 21, sra, 0xffffffff, 0x81818181, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sra, 0xff000000, 0x80000000, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffe0000, 0x80000000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sra, 0xff000000, 0x80000000, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffe0000, 0x80000000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffff, 0x80000000, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xff000000, 0x80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xff000000, 0x80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xff000000, 0x80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffe0000, 0x80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffff, 0x80000000, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xff000000, 0x80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffe0000, 0x80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffff, 0x80000000, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sra, 0 );
+  TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/sra.o b/picorv32_firmware/tests/sra.o
new file mode 100644
index 0000000..daceee0
Binary files /dev/null and b/picorv32_firmware/tests/sra.o differ
diff --git a/picorv32_firmware/tests/srai.S b/picorv32_firmware/tests/srai.S
new file mode 100644
index 0000000..4638190
--- /dev/null
+++ b/picorv32_firmware/tests/srai.S
@@ -0,0 +1,68 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srai.S
+#-----------------------------------------------------------------------------
+#
+# Test srai instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  srai, 0x00000000, 0x00000000, 0  );
+  TEST_IMM_OP( 3,  srai, 0xc0000000, 0x80000000, 1  );
+  TEST_IMM_OP( 4,  srai, 0xff000000, 0x80000000, 7  );
+  TEST_IMM_OP( 5,  srai, 0xfffe0000, 0x80000000, 14 );
+  TEST_IMM_OP( 6,  srai, 0xffffffff, 0x80000001, 31 );
+
+  TEST_IMM_OP( 7,  srai, 0x7fffffff, 0x7fffffff, 0  );
+  TEST_IMM_OP( 8,  srai, 0x3fffffff, 0x7fffffff, 1  );
+  TEST_IMM_OP( 9,  srai, 0x00ffffff, 0x7fffffff, 7  );
+  TEST_IMM_OP( 10, srai, 0x0001ffff, 0x7fffffff, 14 );
+  TEST_IMM_OP( 11, srai, 0x00000000, 0x7fffffff, 31 );
+
+  TEST_IMM_OP( 12, srai, 0x81818181, 0x81818181, 0  );
+  TEST_IMM_OP( 13, srai, 0xc0c0c0c0, 0x81818181, 1  );
+  TEST_IMM_OP( 14, srai, 0xff030303, 0x81818181, 7  );
+  TEST_IMM_OP( 15, srai, 0xfffe0606, 0x81818181, 14 );
+  TEST_IMM_OP( 16, srai, 0xffffffff, 0x81818181, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xff000000, 0x80000000, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xff000000, 0x80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffe0000, 0x80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffff, 0x80000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xff000000, 0x80000000, 7 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffe0000, 0x80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffff, 0x80000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, srai, 0, 31 );
+  TEST_IMM_ZERODEST( 25, srai, 33, 20 );
+#
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/srai.o b/picorv32_firmware/tests/srai.o
new file mode 100644
index 0000000..87b975b
Binary files /dev/null and b/picorv32_firmware/tests/srai.o differ
diff --git a/picorv32_firmware/tests/srl.S b/picorv32_firmware/tests/srl.S
new file mode 100644
index 0000000..35cc4c7
--- /dev/null
+++ b/picorv32_firmware/tests/srl.S
@@ -0,0 +1,90 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srl.S
+#-----------------------------------------------------------------------------
+#
+# Test srl instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  srl, 0xffff8000, 0xffff8000, 0  );
+  TEST_RR_OP( 3,  srl, 0x7fffc000, 0xffff8000, 1  );
+  TEST_RR_OP( 4,  srl, 0x01ffff00, 0xffff8000, 7  );
+  TEST_RR_OP( 5,  srl, 0x0003fffe, 0xffff8000, 14 );
+  TEST_RR_OP( 6,  srl, 0x0001ffff, 0xffff8001, 15 );
+
+  TEST_RR_OP( 7,  srl, 0xffffffff, 0xffffffff, 0  );
+  TEST_RR_OP( 8,  srl, 0x7fffffff, 0xffffffff, 1  );
+  TEST_RR_OP( 9,  srl, 0x01ffffff, 0xffffffff, 7  );
+  TEST_RR_OP( 10, srl, 0x0003ffff, 0xffffffff, 14 );
+  TEST_RR_OP( 11, srl, 0x00000001, 0xffffffff, 31 );
+
+  TEST_RR_OP( 12, srl, 0x21212121, 0x21212121, 0  );
+  TEST_RR_OP( 13, srl, 0x10909090, 0x21212121, 1  );
+  TEST_RR_OP( 14, srl, 0x00424242, 0x21212121, 7  );
+  TEST_RR_OP( 15, srl, 0x00008484, 0x21212121, 14 );
+  TEST_RR_OP( 16, srl, 0x00000000, 0x21212121, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, srl, 0x21212121, 0x21212121, 0xffffffe0 );
+  TEST_RR_OP( 18, srl, 0x10909090, 0x21212121, 0xffffffe1 );
+  TEST_RR_OP( 19, srl, 0x00424242, 0x21212121, 0xffffffe7 );
+  TEST_RR_OP( 20, srl, 0x00008484, 0x21212121, 0xffffffee );
+  TEST_RR_OP( 21, srl, 0x00000000, 0x21212121, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, srl, 0x7fffc000, 0xffff8000, 1  );
+  TEST_RR_SRC2_EQ_DEST( 23, srl, 0x0003fffe, 0xffff8000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1  );
+  TEST_RR_DEST_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x7fffc000, 0xffff8000, 1  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x7fffc000, 0xffff8000, 1  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x7fffc000, 0xffff8000, 1  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x01ffff00, 0xffff8000, 7 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x0001ffff, 0xffff8000, 15 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x7fffc000, 0xffff8000, 1  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x01ffff00, 0xffff8000, 7 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x0001ffff, 0xffff8000, 15 );
+
+  TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, srl, 0 );
+  TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/srl.o b/picorv32_firmware/tests/srl.o
new file mode 100644
index 0000000..347b6be
Binary files /dev/null and b/picorv32_firmware/tests/srl.o differ
diff --git a/picorv32_firmware/tests/srli.S b/picorv32_firmware/tests/srli.S
new file mode 100644
index 0000000..be56dc3
--- /dev/null
+++ b/picorv32_firmware/tests/srli.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srli.S
+#-----------------------------------------------------------------------------
+#
+# Test srli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  srli, 0xffff8000, 0xffff8000, 0  );
+  TEST_IMM_OP( 3,  srli, 0x7fffc000, 0xffff8000, 1  );
+  TEST_IMM_OP( 4,  srli, 0x01ffff00, 0xffff8000, 7  );
+  TEST_IMM_OP( 5,  srli, 0x0003fffe, 0xffff8000, 14 );
+  TEST_IMM_OP( 6,  srli, 0x0001ffff, 0xffff8001, 15 );
+
+  TEST_IMM_OP( 7,  srli, 0xffffffff, 0xffffffff, 0  );
+  TEST_IMM_OP( 8,  srli, 0x7fffffff, 0xffffffff, 1  );
+  TEST_IMM_OP( 9,  srli, 0x01ffffff, 0xffffffff, 7  );
+  TEST_IMM_OP( 10, srli, 0x0003ffff, 0xffffffff, 14 );
+  TEST_IMM_OP( 11, srli, 0x00000001, 0xffffffff, 31 );
+
+  TEST_IMM_OP( 12, srli, 0x21212121, 0x21212121, 0  );
+  TEST_IMM_OP( 13, srli, 0x10909090, 0x21212121, 1  );
+  TEST_IMM_OP( 14, srli, 0x00424242, 0x21212121, 7  );
+  TEST_IMM_OP( 15, srli, 0x00008484, 0x21212121, 14 );
+  TEST_IMM_OP( 16, srli, 0x00000000, 0x21212121, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 21, srli, 0x7fffc000, 0xffff8000, 1  );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 22, 0, srl, 0x7fffc000, 0xffff8000, 1  );
+  TEST_IMM_DEST_BYPASS( 23, 1, srl, 0x0003fffe, 0xffff8000, 14 );
+  TEST_IMM_DEST_BYPASS( 24, 2, srl, 0x0001ffff, 0xffff8000, 15 );
+
+  TEST_IMM_SRC1_BYPASS( 25, 0, srl, 0x7fffc000, 0xffff8000, 1  );
+  TEST_IMM_SRC1_BYPASS( 26, 1, srl, 0x0003fffe, 0xffff8000, 14 );
+  TEST_IMM_SRC1_BYPASS( 27, 2, srl, 0x0001ffff, 0xffff8000, 15 );
+
+
+  TEST_IMM_ZEROSRC1( 28, srli, 0, 31 );
+  TEST_IMM_ZERODEST( 29, srli, 33, 20 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/srli.o b/picorv32_firmware/tests/srli.o
new file mode 100644
index 0000000..dd15fd6
Binary files /dev/null and b/picorv32_firmware/tests/srli.o differ
diff --git a/picorv32_firmware/tests/sub.S b/picorv32_firmware/tests/sub.S
new file mode 100644
index 0000000..ad56e3e
--- /dev/null
+++ b/picorv32_firmware/tests/sub.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sub.S
+#-----------------------------------------------------------------------------
+#
+# Test sub instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sub, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sub, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sub, 0xfffffffc, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  sub, 0x00008000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  sub, 0x80000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  sub, 0x80008000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP( 8,  sub, 0xffff8001, 0x00000000, 0x00007fff );
+  TEST_RR_OP( 9,  sub, 0x7fffffff, 0x7fffffff, 0x00000000 );
+  TEST_RR_OP( 10, sub, 0x7fff8000, 0x7fffffff, 0x00007fff );
+
+  TEST_RR_OP( 11, sub, 0x7fff8001, 0x80000000, 0x00007fff );
+  TEST_RR_OP( 12, sub, 0x80007fff, 0x7fffffff, 0xffff8000 );
+
+  TEST_RR_OP( 13, sub, 0x00000001, 0x00000000, 0xffffffff );
+  TEST_RR_OP( 14, sub, 0xfffffffe, 0xffffffff, 0x00000001 );
+  TEST_RR_OP( 15, sub, 0x00000000, 0xffffffff, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 );
+  TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 );
+  TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 34, sub, 15, -15 );
+  TEST_RR_ZEROSRC2( 35, sub, 32, 32 );
+  TEST_RR_ZEROSRC12( 36, sub, 0 );
+  TEST_RR_ZERODEST( 37, sub, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/sub.o b/picorv32_firmware/tests/sub.o
new file mode 100644
index 0000000..f6beb12
Binary files /dev/null and b/picorv32_firmware/tests/sub.o differ
diff --git a/picorv32_firmware/tests/sw.S b/picorv32_firmware/tests/sw.S
new file mode 100644
index 0000000..fbf76cc
--- /dev/null
+++ b/picorv32_firmware/tests/sw.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sw.S
+#-----------------------------------------------------------------------------
+#
+# Test sw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, lw, sw, 0x00aa00aa, 0,  tdat );
+  TEST_ST_OP( 3, lw, sw, 0xaa00aa00, 4,  tdat );
+  TEST_ST_OP( 4, lw, sw, 0x0aa00aa0, 8,  tdat );
+  TEST_ST_OP( 5, lw, sw, 0xa00aa00a, 12, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, lw, sw, 0x00aa00aa, -12, tdat8 );
+  TEST_ST_OP( 7, lw, sw, 0xaa00aa00, -8,  tdat8 );
+  TEST_ST_OP( 8, lw, sw, 0x0aa00aa0, -4,  tdat8 );
+  TEST_ST_OP( 9, lw, sw, 0xa00aa00a, 0,   tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x3, 0x12345678, \
+    la  x1, tdat9; \
+    li  x2, 0x12345678; \
+    addi x4, x1, -32; \
+    sw x2, 32(x4); \
+    lw x3, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x3, 0x58213098, \
+    la  x1, tdat9; \
+    li  x2, 0x58213098; \
+    addi x1, x1, -3; \
+    sw x2, 7(x1); \
+    la  x4, tdat10; \
+    lw x3, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xaabbccdd, 0,  tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xdaabbccd, 4,  tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xddaabbcc, 8,  tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xcddaabbc, 12, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xccddaabb, 16, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xbccddaab, 20, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0,  tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4,  tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8,  tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .word 0xdeadbeef
+tdat2:  .word 0xdeadbeef
+tdat3:  .word 0xdeadbeef
+tdat4:  .word 0xdeadbeef
+tdat5:  .word 0xdeadbeef
+tdat6:  .word 0xdeadbeef
+tdat7:  .word 0xdeadbeef
+tdat8:  .word 0xdeadbeef
+tdat9:  .word 0xdeadbeef
+tdat10: .word 0xdeadbeef
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/sw.o b/picorv32_firmware/tests/sw.o
new file mode 100644
index 0000000..d3a9160
Binary files /dev/null and b/picorv32_firmware/tests/sw.o differ
diff --git a/picorv32_firmware/tests/test_macros.h b/picorv32_firmware/tests/test_macros.h
new file mode 100644
index 0000000..05ed7c8
--- /dev/null
+++ b/picorv32_firmware/tests/test_macros.h
@@ -0,0 +1,585 @@
+// See LICENSE for license details.
+
+#ifndef __TEST_MACROS_SCALAR_H
+#define __TEST_MACROS_SCALAR_H
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+
+#define TEST_CASE( testnum, testreg, correctval, code... ) \
+test_ ## testnum: \
+    code; \
+    li  x29, correctval; \
+    li  TESTNUM, testnum; \
+    bne testreg, x29, fail;
+
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+
+#define TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
+#define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
+#define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
+#define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
+#define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
+#define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
+#define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
+#define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
+#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x1, val1; \
+      inst x3, x1, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, x1, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      inst x3, x1, SEXT_IMM(imm); \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x3, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      inst x3, x1, SEXT_IMM(imm); \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
+    TEST_CASE( testnum, x0, 0, \
+      li  x1, val1; \
+      inst x0, x1, SEXT_IMM(imm); \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for vector config instructions
+#-----------------------------------------------------------------------
+
+#define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
+    TEST_CASE( testnum, x1, result, \
+      li x1, (bank << 12); \
+      vsetcfg x1,nxpr,nfpr; \
+      li x1, vl; \
+      vsetvl x1,x1; \
+    )
+
+#define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
+    TEST_CASE( testnum, x1, result, \
+      li x1, (bank << 12) | (nfpr << 6) | nxpr; \
+      vsetcfg x1; \
+      li x1, vl; \
+      vsetvl x1,x1; \
+    )
+
+#define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
+    TEST_CASE( testnum, x1, result, \
+      li x1, (bank << 12); \
+      vsetcfg x1,nxpr,nfpr; \
+      li x1, vl; \
+      vsetvl x1, x1; \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+
+#define TEST_R_OP( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x1, val1; \
+      inst x3, x1; \
+    )
+
+#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, x1; \
+    )
+
+#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      inst x3, x1; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x3, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+
+#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x3, x1, x2; \
+    )
+
+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x1, x1, x2; \
+    )
+
+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x2, result, \
+      li  x1, val1; \
+      li  x2, val2; \
+      inst x2, x1, x2; \
+    )
+
+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, x1, x1; \
+    )
+
+#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      li  x2, val2; \
+      inst x3, x1, x2; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x3, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x2, val2; \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x3, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x3, result, \
+      li  x4, 0; \
+1:    li  x2, val2; \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x1, val1; \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x3, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, val; \
+      inst x2, x0, x1; \
+    )
+
+#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, val; \
+      inst x2, x1, x0; \
+    )
+
+#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, x0; \
+    )
+
+#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
+    TEST_CASE( testnum, x0, 0, \
+      li x1, val1; \
+      li x2, val2; \
+      inst x0, x1, x2; \
+    )
+
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+
+#define TEST_LD_OP( testnum, inst, result, offset, base ) \
+    TEST_CASE( testnum, x3, result, \
+      la  x1, base; \
+      inst x3, offset(x1); \
+    )
+
+#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
+    TEST_CASE( testnum, x3, result, \
+      la  x1, base; \
+      li  x2, result; \
+      store_inst x2, offset(x1); \
+      load_inst x3, offset(x1); \
+    )
+
+#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x1, base; \
+    inst x3, offset(x1); \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    addi  x6, x3, 0; \
+    li  x29, result; \
+    bne x6, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b; \
+
+#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x1, base; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x3, offset(x1); \
+    li  x29, result; \
+    bne x3, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x1, result; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    la  x2, base; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x3, offset(x2); \
+    li  x29, result; \
+    bne x3, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x2, base; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, result; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x3, offset(x2); \
+    li  x29, result; \
+    bne x3, x29, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test branch instructions
+#-----------------------------------------------------------------------
+
+#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    inst x1, 2f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
+2:  inst x1, 1b; \
+    bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    inst x1, 1f; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
+2:  inst x1, 1b; \
+3:
+
+#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x1, val1; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x1, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 2f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
+2:  inst x1, x2, 1b; \
+    bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 1f; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
+2:  inst x1, x2, 1b; \
+3:
+
+#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+
+#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x6; \
+    bne x0, TESTNUM, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x19, x6, 0; \
+    bne x0, TESTNUM, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+
+#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  flw f0, 0(a0); \
+  flw f1, 4(a0); \
+  flw f2, 8(a0); \
+  lw  a3, 12(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne a1, a2, fail; \
+  j 2f; \
+  .align 2; \
+  .data; \
+  test_ ## testnum ## _data: \
+  .float val1; \
+  .float val2; \
+  .float val3; \
+  .result; \
+  .text; \
+2:
+
+#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  fld f0, 0(a0); \
+  fld f1, 8(a0); \
+  fld f2, 16(a0); \
+  ld  a3, 24(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne a1, a2, fail; \
+  j 2f; \
+  .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double val1; \
+  .double val2; \
+  .double val3; \
+  .result; \
+  .text; \
+2:
+
+#define TEST_FCVT_S_D( testnum, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
+
+#define TEST_FCVT_D_S( testnum, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
+                    fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fmv.x.s a0, f3)
+
+#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fmv.x.d a0, f3)
+
+#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fmv.x.s a0, f3)
+
+#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fmv.x.d a0, f3)
+
+#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_CMP_OP_S( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, 0, word result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_FP_CMP_OP_D( testnum, inst, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, 0, dword result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  lw  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  fsflags x0; \
+  fmv.x.s a0, f0; \
+  bne a0, a3, fail; \
+  j 1f; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float result; \
+1:
+
+#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  ld  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  fsflags x0; \
+  fmv.x.d a0, f0; \
+  bne a0, a3, fail; \
+  j 1f; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double result; \
+1:
+
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in TESTNUM)
+#-----------------------------------------------------------------------
+
+#define TEST_PASSFAIL \
+        bne x0, TESTNUM, pass; \
+fail: \
+        RVTEST_FAIL; \
+pass: \
+        RVTEST_PASS \
+
+
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+
+#define TEST_DATA
+
+#endif
diff --git a/picorv32_firmware/tests/xor.S b/picorv32_firmware/tests/xor.S
new file mode 100644
index 0000000..72875fe
--- /dev/null
+++ b/picorv32_firmware/tests/xor.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# xor.S
+#-----------------------------------------------------------------------------
+#
+# Test xor instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 9,  0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 );
+  TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff );
+  TEST_RR_ZEROSRC12( 26, xor, 0 );
+  TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/xor.o b/picorv32_firmware/tests/xor.o
new file mode 100644
index 0000000..23bef9d
Binary files /dev/null and b/picorv32_firmware/tests/xor.o differ
diff --git a/picorv32_firmware/tests/xori.S b/picorv32_firmware/tests/xori.S
new file mode 100644
index 0000000..7f2207c
--- /dev/null
+++ b/picorv32_firmware/tests/xori.S
@@ -0,0 +1,55 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# xori.S
+#-----------------------------------------------------------------------------
+#
+# Test xori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2, xori, 0xff00f00f, 0x00ff0f00, 0xf0f );
+  TEST_IMM_OP( 3, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 );
+  TEST_IMM_OP( 4, xori, 0x00ff0ff0, 0x00ff08ff, 0x70f );
+  TEST_IMM_OP( 5, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xff00f00f, 0xff00f700, 0x70f );
+
+   #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 7,  0, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 );
+  TEST_IMM_DEST_BYPASS( 8,  1, xori, 0x00ff0ff0, 0x00ff08ff, 0x70f );
+  TEST_IMM_DEST_BYPASS( 9,  2, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+  TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x0ff00f00, 0x0ff00ff0, 0x0f0 );
+  TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x00ff0ff0, 0x00ff0fff, 0x00f );
+  TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xf00ff0ff, 0xf00ff00f, 0x0f0 );
+
+  TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 );
+  TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/picorv32_firmware/tests/xori.o b/picorv32_firmware/tests/xori.o
new file mode 100644
index 0000000..c410201
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