From c7fc57213c17289fdb8c8eaa23fcbb61a28b8340 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Sun, 29 Oct 2023 22:25:50 +0100 Subject: [PATCH] Avoid releasing trap signal too early The trap signal is used my the mux in serv_rf_if to decide which registers to write to. If the trap signal is dropped too early, the destination address changes while the register is still being written to. --- rtl/serv_csr.v | 4 ++-- rtl/serv_state.v | 7 ++----- rtl/serv_top.v | 2 +- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/rtl/serv_csr.v b/rtl/serv_csr.v index 7e4bb39..1bcfc06 100644 --- a/rtl/serv_csr.v +++ b/rtl/serv_csr.v @@ -5,7 +5,7 @@ module serv_csr input wire i_clk, input wire i_rst, //State - input wire i_init, + input wire i_trig_irq, input wire i_en, input wire i_cnt0to3, input wire i_cnt3, @@ -74,7 +74,7 @@ module serv_csr assign o_csr_in = csr_in; always @(posedge i_clk) begin - if (!i_init & i_cnt_done) begin + if (i_trig_irq) begin timer_irq_r <= timer_irq; o_new_irq <= timer_irq & !timer_irq_r; end diff --git a/rtl/serv_state.v b/rtl/serv_state.v index 271eb9d..68e6eb0 100644 --- a/rtl/serv_state.v +++ b/rtl/serv_state.v @@ -213,11 +213,8 @@ module serv_state (i_dbus_en & i_mem_misalign)); always @(posedge i_clk) begin - if (o_cnt_done) - misalign_trap_sync_r <= trap_pending & o_init; - if (i_rst) - if (RESET_STRATEGY != "NONE") - misalign_trap_sync_r <= 1'b0; + if (i_ibus_ack | o_cnt_done | i_rst) + misalign_trap_sync_r <= !(i_ibus_ack | i_rst) & ((trap_pending & o_init) | misalign_trap_sync_r); end assign misalign_trap_sync = misalign_trap_sync_r; end else diff --git a/rtl/serv_top.v b/rtl/serv_top.v index fd9c038..1e55b02 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -541,7 +541,7 @@ module serv_top .i_clk (clk), .i_rst (i_rst), //State - .i_init (init), + .i_trig_irq (wb_ibus_ack), .i_en (cnt_en), .i_cnt0to3 (cnt0to3), .i_cnt3 (cnt3),