From c9f41b54e8dc93aa798f466c93f10d84421270bb Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Tue, 22 Dec 2020 21:52:45 +0100 Subject: [PATCH] Optimize init signal --- rtl/serv_alu.v | 3 +-- rtl/serv_bufreg.v | 4 ++-- rtl/serv_state.v | 29 +++++++++++------------------ rtl/serv_top.v | 1 - 4 files changed, 14 insertions(+), 23 deletions(-) diff --git a/rtl/serv_alu.v b/rtl/serv_alu.v index eeb021c..aa307bf 100644 --- a/rtl/serv_alu.v +++ b/rtl/serv_alu.v @@ -10,7 +10,6 @@ module serv_alu input wire i_imm, input wire i_op_b_rs2, input wire i_buf, - input wire i_init, input wire i_cnt_done, input wire i_sub, input wire [1:0] i_bool_op, @@ -41,7 +40,7 @@ module serv_alu serv_shift shift ( .i_clk (clk), - .i_load (i_init), + .i_load (i_cnt_done), .i_shamt (shamt), .i_shamt_msb (shamt_msb), .i_signbit (i_sh_signed & i_rs1), diff --git a/rtl/serv_bufreg.v b/rtl/serv_bufreg.v index 1f8c70c..0c37d69 100644 --- a/rtl/serv_bufreg.v +++ b/rtl/serv_bufreg.v @@ -24,8 +24,8 @@ module serv_bufreg assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r; always @(posedge i_clk) begin - //Clear carry when not in INIT state - c_r <= c & i_init; + //Make sure carry is cleared before loading new data + c_r <= c & i_en; if (i_en) data <= {(i_loop & !i_init) ? o_q : q, data[31:1]}; diff --git a/rtl/serv_state.v b/rtl/serv_state.v index 19b192b..95e37d6 100644 --- a/rtl/serv_state.v +++ b/rtl/serv_state.v @@ -23,7 +23,7 @@ module serv_state input wire i_slt_op, input wire i_e_op, input wire i_rd_op, - output reg o_init, + output wire o_init, output reg o_cnt_en, output wire o_cnt0, output wire o_cnt0to3, @@ -80,9 +80,7 @@ module serv_state //slt*, branch/jump, shift, load/store wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op; - reg stage_two_pending; - - assign o_dbus_cyc = !o_cnt_en & stage_two_pending & i_mem_op & !i_mem_misalign; + assign o_dbus_cyc = !o_cnt_en & init_done & i_mem_op & !i_mem_misalign; wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign); @@ -91,7 +89,7 @@ module serv_state assign o_rf_rreq = i_ibus_ack | (stage_two_req & trap_pending); //Prepare RF for writes when everything is ready to enter stage two - assign o_rf_wreq = ((i_shift_op & i_alu_sh_done & stage_two_pending) | (i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op))) & !trap_pending; + assign o_rf_wreq = ((i_shift_op & i_alu_sh_done & init_done) | (i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op))) & !trap_pending; assign o_rf_rd_en = i_rd_op & o_cnt_en & !o_init; @@ -103,6 +101,9 @@ module serv_state assign o_ibus_cyc = ibus_cyc & !i_rst; + assign o_init = two_stage_op & !o_pending_irq & !init_done; + reg init_done; + always @(posedge i_clk) begin //ibus_cyc changes on three conditions. //1. i_rst is asserted. Together with the async gating above, o_ibus_cyc @@ -116,23 +117,15 @@ module serv_state if (i_ibus_ack | o_cnt_done | i_rst) ibus_cyc <= o_ctrl_pc_en | i_rst; - if (o_cnt_done) - o_ctrl_jump <= o_init & take_branch; - - if (o_cnt_en) - stage_two_pending <= o_init; - + if (o_cnt_done) begin + init_done <= o_init & !init_done; + o_ctrl_jump <= o_init & take_branch; + end o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2]; //Need a strobe for the first cycle in the IDLE state after INIT stage_two_req <= o_cnt_done & o_init; - if (i_rf_ready & !stage_two_pending) - o_init <= two_stage_op & !o_pending_irq; - - if (o_cnt_done) - o_init <= 1'b0; - if (i_rf_ready) o_cnt_en <= 1'b1; @@ -147,7 +140,7 @@ module serv_state if (RESET_STRATEGY != "NONE") begin o_cnt_en <= 1'b0; o_cnt <= 3'd0; - stage_two_pending <= 1'b0; + init_done <= 1'b0; o_ctrl_jump <= 1'b0; o_cnt_r <= 4'b0001; end diff --git a/rtl/serv_top.v b/rtl/serv_top.v index 22fae9c..3c443d9 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -331,7 +331,6 @@ module serv_top //State .i_en (cnt_en), .i_cnt0 (cnt0), - .i_init (init), .i_cnt_done (cnt_done), .i_shamt_en (alu_shamt_en), .o_cmp (alu_cmp),