From ca2beaf786c39d420eb145b82fe3dac6f352766f Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Mon, 16 Sep 2019 20:54:26 +0200 Subject: [PATCH] Pass rf_rreq through serv_state --- rtl/serv_state.v | 4 ++++ rtl/serv_top.v | 5 ++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/rtl/serv_state.v b/rtl/serv_state.v index e12c112..eec07cb 100644 --- a/rtl/serv_state.v +++ b/rtl/serv_state.v @@ -4,6 +4,8 @@ module serv_state input wire i_rst, input wire i_new_irq, input wire i_dbus_ack, + input wire i_ibus_ack, + output wire o_rf_rreq, input wire i_rf_ready, input wire i_take_branch, input wire i_branch_op, @@ -84,6 +86,8 @@ module serv_state assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !mem_misalign; + assign o_rf_rreq = i_ibus_ack; + always @(posedge i_clk) begin if (state == INIT) o_ctrl_jump <= i_take_branch; diff --git a/rtl/serv_top.v b/rtl/serv_top.v index 84e7a18..5b5fd98 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -98,6 +98,7 @@ module serv_top wire alu_sh_done; wire [1:0] alu_rd_sel; + wire rf_rreq; wire rf_ready; wire rs1; wire rs2; @@ -141,6 +142,8 @@ module serv_top .i_rst (i_rst), .i_new_irq (new_irq), .i_dbus_ack (i_dbus_ack), + .i_ibus_ack (i_ibus_ack), + .o_rf_rreq (rf_rreq), .i_rf_ready (rf_ready), .i_take_branch (take_branch), .i_branch_op (branch_op), @@ -341,7 +344,7 @@ module serv_top .i_rd_waddr (rd_addr), .i_rd (rd), - .i_rreq (i_ibus_ack), + .i_rreq (rf_rreq), .o_rgnt (rf_ready), //RS1 read port .i_rs1_raddr (rs1_addr),