From d4102f927fc62c1f40e72a1a35b6272381622cf8 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Sat, 17 Nov 2018 22:14:44 +0100
Subject: [PATCH] Synthesis fixes

---
 bench/serv_wrapper.v | 28 +++++++++++++++++++++++-----
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/bench/serv_wrapper.v b/bench/serv_wrapper.v
index 43dc89a..62e06f1 100644
--- a/bench/serv_wrapper.v
+++ b/bench/serv_wrapper.v
@@ -1,10 +1,18 @@
 `default_nettype none
 module serv_wrapper
 (
- input wire wb_clk,
- input wire wb_rst);
+ input wire wb_clk);
 
-   parameter firmware = "firmware.hex";
+//   parameter memfile = "hellomin.hex";
+   parameter memfile = "bitbang.hex";
+
+
+   reg [4:0] rst_reg = 5'b11111;
+
+   always @(posedge wb_clk)
+     rst_reg <= {1'b0, rst_reg[4:1]};
+
+   wire      wb_rst = rst_reg[0];
 
    wire 	timer_irq;
 
@@ -12,16 +20,22 @@ module serv_wrapper
 
    localparam MEMORY_SIZE = 16384*4;
 
+`ifndef SYNTHESIS
+//synthesis translate_off
    reg [1023:0] firmware_file;
    initial
      if ($value$plusargs("firmware=%s", firmware_file)) begin
 	$display("Loading RAM from %0s", firmware_file);
 	$readmemh(firmware_file, ram.ram0.mem);
      end
-
+//synthesis translate_on
+`endif
 
    wb_ram
-     #(/*.memfile (firmware),*/
+     #(
+`ifdef SYNTHESIS
+.memfile (memfile),
+`endif
        .depth (MEMORY_SIZE))
    ram
      (// Wishbone interface
@@ -48,6 +62,8 @@ module serv_wrapper
       .i_wb_stb   (wb_m2s_testprint_stb),
       .o_wb_ack   (wb_s2m_testprint_ack));
 
+   assign wb_s2m_testprint_dat = 32'h0;
+   
    testhalt testhalt
      (
       .i_wb_clk   (wb_clk),
@@ -57,6 +73,8 @@ module serv_wrapper
       .i_wb_stb   (wb_m2s_testhalt_stb),
       .o_wb_ack   (wb_s2m_testhalt_ack));
 
+   assign wb_s2m_testhalt_dat = 32'h0;
+
    riscv_timer riscv_timer
      (.i_clk    (wb_clk),
       .o_irq    (timer_irq),