Rewrite register file

2026-04-24 19:40:55 +00:00 · 2018-11-26 00:09:52 +01:00
parent a974320f46
commit e1f5bcc4f3
6 changed files with 64 additions and 1333 deletions
--- a/cores/techlibs/cells_sim.v
+++ b/cores/techlibs/cells_sim.v
--- a/cores/techlibs/ice40-0.7.core
+++ b/cores/techlibs/ice40-0.7.core
@@ -1,12 +0,0 @@
-CAPI=2:
-
-name : yosys:techlibs:ice40fork:0.7
-
-filesets:
-  ice40_cells:
-    files:
-      - cells_sim.v : {file_type : verilogSource}
-
-targets:
-  default:
-    filesets : [ice40_cells]