From e3e616903e1f729fdde402a44d9b55087b2c4302 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Wed, 12 Dec 2018 22:30:47 +0100 Subject: [PATCH] Optimize bool operations --- rtl/serv_alu.v | 12 +++++++----- rtl/serv_decode.v | 12 ++++++------ rtl/serv_params.vh | 12 +++++------- rtl/serv_top.v | 5 ++++- 4 files changed, 22 insertions(+), 19 deletions(-) diff --git a/rtl/serv_alu.v b/rtl/serv_alu.v index 59dbcc1..89e952e 100644 --- a/rtl/serv_alu.v +++ b/rtl/serv_alu.v @@ -9,6 +9,7 @@ module serv_alu input wire i_init, input wire i_cnt_done, input wire i_sub, + input wire [1:0] i_bool_op, input wire i_cmp_sel, input wire i_cmp_neg, input wire i_cmp_uns, @@ -16,7 +17,7 @@ module serv_alu input wire i_shamt_en, input wire i_sh_right, input wire i_sh_signed, - input wire [2:0] i_rd_sel, + input wire [1:0] i_rd_sel, output wire o_rd); `include "serv_params.vh" @@ -114,13 +115,14 @@ module serv_alu assign plus_1 = i_en & !en_r; assign o_cmp = i_cmp_neg^((i_cmp_sel == ALU_CMP_EQ) ? (result_eq & (i_rs1 == i_op_b)) : result_lt); + localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor + wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, i_op_b}]; + assign o_rd = (i_rd_sel == ALU_RESULT_ADD) ? result_add : (i_rd_sel == ALU_RESULT_SR) ? result_sh : (i_rd_sel == ALU_RESULT_LT) ? (result_lt_r & init_r & ~i_init) : - (i_rd_sel == ALU_RESULT_XOR) ? i_rs1^i_op_b : - (i_rd_sel == ALU_RESULT_OR) ? i_rs1|i_op_b : - (i_rd_sel == ALU_RESULT_AND) ? i_rs1&i_op_b : - 1'bx; + (i_rd_sel == ALU_RESULT_BOOL) ? result_bool : 1'bx; + always @(posedge clk) begin if (i_init) begin diff --git a/rtl/serv_decode.v b/rtl/serv_decode.v index db44ff8..312738d 100644 --- a/rtl/serv_decode.v +++ b/rtl/serv_decode.v @@ -27,6 +27,7 @@ module serv_decode output wire o_alu_en, output wire o_alu_init, output wire o_alu_sub, + output wire [1:0] o_alu_bool_op, output reg o_alu_cmp_sel, output wire o_alu_cmp_neg, output reg o_alu_cmp_uns, @@ -34,7 +35,7 @@ module serv_decode output wire o_alu_shamt_en, output wire o_alu_sh_signed, output wire o_alu_sh_right, - output reg [2:0] o_alu_rd_sel, + output reg [1:0] o_alu_rd_sel, output wire o_mem_en, output wire o_mem_cmd, output wire o_mem_init, @@ -217,18 +218,17 @@ module serv_decode wire jal_misalign = op[21] & opcode[1] & opcode[4]; + assign o_alu_bool_op = o_funct3[1:0]; always @(posedge clk) begin casez(o_funct3) 3'b000 : o_alu_rd_sel <= ALU_RESULT_ADD; 3'b001 : o_alu_rd_sel <= ALU_RESULT_SR; 3'b01? : o_alu_rd_sel <= ALU_RESULT_LT; - 3'b100 : o_alu_rd_sel <= ALU_RESULT_XOR; + 3'b100 : o_alu_rd_sel <= ALU_RESULT_BOOL; 3'b101 : o_alu_rd_sel <= ALU_RESULT_SR; - 3'b110 : o_alu_rd_sel <= ALU_RESULT_OR; - 3'b111 : o_alu_rd_sel <= ALU_RESULT_AND; - //default : o_alu_rd_sel <= 3'bxx; - endcase + 3'b11? : o_alu_rd_sel <= ALU_RESULT_BOOL; + endcase // casez (o_funct3) if (i_wb_en) begin o_rf_rd_addr <= i_wb_rdt[11:7]; diff --git a/rtl/serv_params.vh b/rtl/serv_params.vh index 581eb0b..08ae454 100644 --- a/rtl/serv_params.vh +++ b/rtl/serv_params.vh @@ -6,13 +6,11 @@ localparam [0:0] OP_B_SOURCE_IMM = 1'd0, OP_B_SOURCE_RS2 = 1'd1; -localparam[2:0] - ALU_RESULT_ADD = 3'd0, - ALU_RESULT_SR = 3'd1, - ALU_RESULT_LT = 3'd2, - ALU_RESULT_XOR = 3'd3, - ALU_RESULT_OR = 3'd4, - ALU_RESULT_AND = 3'd5; +localparam[1:0] + ALU_RESULT_ADD = 2'd0, + ALU_RESULT_SR = 2'd1, + ALU_RESULT_LT = 2'd2, + ALU_RESULT_BOOL = 2'd3; localparam [0:0] ALU_CMP_LT = 1'b0, diff --git a/rtl/serv_top.v b/rtl/serv_top.v index 8451b45..76d7368 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -79,6 +79,7 @@ module serv_top wire alu_en; wire alu_init; wire alu_sub; + wire [1:0] alu_bool_op; wire alu_cmp_sel; wire alu_cmp_neg; wire alu_cmp_uns; @@ -86,7 +87,7 @@ module serv_top wire alu_shamt_en; wire alu_sh_signed; wire alu_sh_right; - wire [2:0] alu_rd_sel; + wire [1:0] alu_rd_sel; wire rf_ready; wire rs1; @@ -146,6 +147,7 @@ module serv_top .o_alu_en (alu_en), .o_alu_init (alu_init), .o_alu_sub (alu_sub), + .o_alu_bool_op (alu_bool_op), .o_alu_cmp_sel (alu_cmp_sel), .o_alu_cmp_neg (alu_cmp_neg), .o_alu_cmp_uns (alu_cmp_uns), @@ -218,6 +220,7 @@ module serv_top .i_init (alu_init), .i_cnt_done (cnt_done), .i_sub (alu_sub), + .i_bool_op (alu_bool_op), .i_cmp_sel (alu_cmp_sel), .i_cmp_neg (alu_cmp_neg), .i_cmp_uns (alu_cmp_uns),