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Simplify MDU logic in serv_mem_if

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Olof Kindgren
2021-10-04 23:38:33 +02:00
parent 99f82af6eb
commit e5c6e78820
2 changed files with 2 additions and 12 deletions
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2
rtl/serv_decode.v
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@@ -76,7 +76,7 @@ module serv_decode
wire co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01) & !co_mdu_op; wire co_slt_op = op_or_opimm & (funct3[2:1] == 2'b01) & !co_mdu_op;
wire co_mem_op = !opcode[4] & !opcode[2] & !opcode[0]; wire co_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
wire co_branch_op = opcode[4] & !opcode[2]; wire co_branch_op = opcode[4] & !opcode[2];
wire co_mem_word = co_mdu_op | funct3[1]; wire co_mem_word = funct3[1];
wire co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op; wire co_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4] & !co_mdu_op;
wire [2:0] co_ext_funct3 = funct3; wire [2:0] co_ext_funct3 = funct3;

12
rtl/serv_mem_if.v
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@@ -61,17 +61,7 @@ module serv_mem_if
(i_bytecnt == 2'b00) | (i_bytecnt == 2'b00) |
(i_half & !i_bytecnt[1]); (i_half & !i_bytecnt[1]);
wire mem_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed); assign o_rd = (i_mem_op | i_mdu_op) & ((dat_valid|i_mdu_op) ? dat_cur : signbit & i_signed);
generate
if(MDU) begin
wire mdu_rd = i_mdu_op & dat_cur;
assign o_rd = mem_rd | mdu_rd;
end else begin
wire mdu_rd = 1'b0;
assign o_rd = mem_rd;
end
endgenerate
assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]); assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]);
assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word; assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word;