diff --git a/rtl/serv_alu.v b/rtl/serv_alu.v
index 8a1261b..b934c55 100644
--- a/rtl/serv_alu.v
+++ b/rtl/serv_alu.v
@@ -5,7 +5,9 @@ module serv_alu
    input wire 	    i_rst,
    input wire 	    i_en,
    input wire 	    i_rs1,
-   input wire 	    i_op_b,
+   input wire 	    i_rs2,
+   input wire 	    i_imm,
+   input wire 	    i_op_b_rs2,
    input wire 	    i_buf,
    input wire 	    i_init,
    input wire 	    i_cnt_done,
@@ -38,7 +40,8 @@ module serv_alu
    wire        plus_1;
    wire        b_inv_plus_1;
 
-   assign shamt_ser = i_sh_right ? i_op_b : b_inv_plus_1;
+   wire op_b = i_op_b_rs2 ? i_rs2 : i_imm;
+   assign shamt_ser = i_sh_right ? op_b : b_inv_plus_1;
 
    shift_reg #(.LEN (5)) shamt_reg
      (.clk (clk),
@@ -70,13 +73,13 @@ module serv_alu
      (
       .clk (clk),
       .rst (i_rst),
-      .a   (~i_op_b),
+      .a   (~op_b),
       .b   (plus_1),
       .clr (!i_en),
       .q   (b_inv_plus_1),
       .o_v (b_inv_plus_1_cy));
 
-   wire       add_b = i_sub ? b_inv_plus_1 : i_op_b;
+   wire       add_b = i_sub ? b_inv_plus_1 : op_b;
 
    ser_add ser_add
      (
@@ -92,7 +95,7 @@ module serv_alu
      (
       .i_clk (clk),
       .i_a   (i_rs1),
-      .i_b   (i_op_b),
+      .i_b   (op_b),
       .i_clr (!i_en),
       .i_sign (i_cnt_done & !i_cmp_uns),
       .o_q   (result_lt));
@@ -101,7 +104,7 @@ module serv_alu
    assign o_cmp = i_cmp_eq ? result_eq : result_lt;
 
    localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor
-   wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, i_op_b}];
+   wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, op_b}];
 
    assign o_rd = (i_rd_sel == ALU_RESULT_ADD) ? result_add :
                  (i_rd_sel == ALU_RESULT_SR)  ? result_sh :
@@ -119,6 +122,6 @@ module serv_alu
       en_r <= i_en;
    end
 
-   assign result_eq = eq_r & (i_rs1 == i_op_b);
+   assign result_eq = eq_r & (i_rs1 == op_b);
 
 endmodule
diff --git a/rtl/serv_params.vh b/rtl/serv_params.vh
index 7d1e518..25bf9ca 100644
--- a/rtl/serv_params.vh
+++ b/rtl/serv_params.vh
@@ -1,7 +1,3 @@
-localparam [0:0]
-  OP_B_SOURCE_IMM = 1'd0,
-  OP_B_SOURCE_RS2 = 1'd1;
-
 localparam[1:0]
   ALU_RESULT_ADD  = 2'd0,
   ALU_RESULT_SR   = 2'd1,
diff --git a/rtl/serv_top.v b/rtl/serv_top.v
index fe9bfe1..69165d0 100644
--- a/rtl/serv_top.v
+++ b/rtl/serv_top.v
@@ -55,8 +55,6 @@ module serv_top
    input wire [31:0]  i_dbus_rdt,
    input wire 	      i_dbus_ack);
 
-`include "serv_params.vh"
-
    wire [4:0]    rd_addr;
    wire [4:0]    rs1_addr;
    wire [4:0]    rs2_addr;
@@ -212,6 +210,7 @@ module serv_top
       .o_ctrl_pc_rel      (pc_rel),
       .o_ctrl_mret        (mret),
       //To alu
+      .o_op_b_source      (op_b_source),
       .o_alu_sub          (alu_sub),
       .o_alu_bool_op      (alu_bool_op),
       .o_alu_cmp_eq       (alu_cmp_eq),
@@ -239,7 +238,6 @@ module serv_top
       .o_csr_d_sel        (csr_d_sel),
       //To top
       .o_imm              (imm),
-      .o_op_b_source      (op_b_source),
       .o_rd_csr_en        (rd_csr_en),
       .o_rd_alu_en        (rd_alu_en));
 
@@ -291,7 +289,6 @@ module serv_top
       .o_ibus_cyc (o_ibus_cyc),
       .i_ibus_ack (i_ibus_ack));
 
-   assign op_b = (op_b_source == OP_B_SOURCE_IMM) ? imm : rs2;
 
    serv_alu alu
      (
@@ -299,7 +296,9 @@ module serv_top
       .i_rst      (i_rst),
       .i_en       (cnt_en),
       .i_rs1      (rs1),
-      .i_op_b     (op_b),
+      .i_rs2      (rs2),
+      .i_imm      (imm),
+      .i_op_b_rs2 (op_b_source),
       .i_buf      (bufreg_q),
       .i_init     (init),
       .i_cnt_done (cnt_done),