Syntax fixes to please Vivado

2026-02-26 00:03:45 +00:00 · 2018-12-07 23:20:47 +01:00
parent 468e99ac7c
commit f627aee1a1
1 changed files with 3 additions and 3 deletions
--- a/rtl/serv_clock_gen.v
+++ b/rtl/serv_clock_gen.v
@@ -1,9 +1,9 @@
 `default_nettype none
 module serv_clock_gen
  (
-   input  i_clk,
-   output o_clk,
-   output o_rst);
+   input wire  i_clk,
+   output wire o_clk,
+   output wire o_rst);

   parameter PLL = "NONE";