Add explicit wire defs to ports

testprint.v

@@ -1,20 +1,21 @@
 `default_nettype none
 module testprint
   (
-   input        i_wb_clk,
+   input wire        i_wb_clk,
+   input wire [31:0] i_wb_dat,
+   input wire        i_wb_we,
+   input wire        i_wb_cyc,
+   input wire        i_wb_stb,
+   output reg   o_wb_ack = 1'b0);
 
-   input [31:0] i_wb_dat,
-   input        i_wb_we,
-   input        i_wb_cyc,
-   input        i_wb_stb,
-   output reg   o_wb_ack  /* verilator public */ = 1'b0);
+   wire 	wb_en;
 
-   wire 	wb_en /* verilator public */;
-
-   wire [7:0]	ch /* verilator public */;
+   wire [7:0]	ch;
    assign ch = i_wb_dat[7:0];
 
    assign wb_en = i_wb_cyc & i_wb_stb;
+`ifndef SYNTHESIS
+   //synthesis translate_off
    reg [1023:0] signature_file;
    integer 	f = 0;
 
@@ -23,9 +24,12 @@ module testprint
 	$display("Writing signature to %0s", signature_file);
 	f = $fopen(signature_file, "w");
      end
-
+   //synthesis translate_on
+`endif
    always @(posedge i_wb_clk) begin
       o_wb_ack <= 1'b0;
+`ifndef SYNTHESIS
+   //synthesis translate_off
       if (wb_en & o_wb_ack) begin
 	 if (f)
 	   $fwrite(f, "%c", i_wb_dat[7:0]);
@@ -34,6 +38,8 @@ module testprint
          $fflush();
 `endif
       end
+   //synthesis translate_on
+`endif
       if (wb_en & !o_wb_ack)
         o_wb_ack <= 1'b1;
    end