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Add cyc1000 target

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This commit is contained in:
Olof Kindgren
2019-10-21 15:24:33 +02:00
parent e39b4770fd
commit fca1527dd7
5 changed files with 121 additions and 0 deletions
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8
data/cyc1000.sdc Normal file
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# Main system clock (12 Mhz)
create_clock -name "clk" -period 83.333ns [get_ports {i_clk}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

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data/cyc1000.tcl Normal file
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#
# Clock / Reset
#
set_location_assignment PIN_M2 -to i_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
set_location_assignment PIN_N6 -to i_rst
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i_clk
#UART/GPIO
set_location_assignment PIN_M6 -to q
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
set_location_assignment PIN_T7 -to uart_txd
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart*