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Optimize enable signal for mem_if buffers

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Olof Kindgren
2020-04-14 16:54:05 +02:00
parent 1d311edb7d
commit fda7dd288a
2 changed files with 16 additions and 37 deletions
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52
rtl/serv_mem_if.v
View File

@@ -4,7 +4,6 @@ module serv_mem_if
(
input wire i_clk,
input wire i_en,
input wire i_init,
input wire i_mem_op,
input wire i_signed,
input wire i_word,
@@ -22,54 +21,35 @@ module serv_mem_if
reg signbit;
reg [7:0] dat0;
reg [7:0] dat1;
reg [7:0] dat2;
reg [7:0] dat3;
wire dat0_en;
wire dat1_en;
wire dat2_en;
wire dat3_en;
wire [2:0] tmp = {1'b0,i_bytecnt}+{1'b0,i_lsb};
wire [1:0] dat_sel = i_bytecnt[1] ? i_bytecnt : (i_bytecnt | i_lsb);
reg [31:0] dat;
wire dat_cur = (dat_sel == 3) ? dat3[0] :
(dat_sel == 2) ? dat2[0] :
(dat_sel == 1) ? dat1[0] : dat0[0];
wire dat_en = i_en & !tmp[2];
wire dat_cur =
((i_lsb == 2'd3) & dat[24]) |
((i_lsb == 2'd2) & dat[16]) |
((i_lsb == 2'd1) & dat[8]) |
((i_lsb == 2'd0) & dat[0]);
wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]);
assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed);
assign o_wb_sel[3] = i_word | (i_half & i_lsb[1]) | (i_lsb == 2'b11);
assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]);
assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word;
assign o_wb_sel[1] = ((i_word | i_half) & !i_lsb[1]) | (i_lsb == 2'b01);
assign o_wb_sel[1] = (i_lsb == 2'b01) | i_word | (i_half & !i_lsb[1]);
assign o_wb_sel[0] = (i_lsb == 2'b00);
wire wbyte0 = (i_bytecnt == 2'b00);
wire wbyte1 = ((i_bytecnt == 2'b01) & !i_lsb[0]);
wire wbyte2 = ((i_bytecnt == 2'b10) & !i_lsb[1]);
wire wbyte3 = ((i_bytecnt == 2'b11) & !i_lsb[1]);
assign dat0_en = i_en & (i_init ? wbyte0 : (dat_sel == 2'd0));
assign dat1_en = i_en & (i_init ? (wbyte0 | wbyte1) : (dat_sel == 2'd1));
assign dat2_en = i_en & (i_init ? (wbyte0 | wbyte2) : (dat_sel == 2'd2));
assign dat3_en = i_en & (i_init ? (wbyte0 | wbyte1 | wbyte3) : (dat_sel == 2'd3));
assign o_wb_dat = {dat3,dat2,dat1,dat0};
assign o_wb_dat = dat;
always @(posedge i_clk) begin
if (dat0_en)
dat0 <= {i_rs2, dat0[7:1]};
if (dat1_en)
dat1 <= {i_rs2, dat1[7:1]};
if (dat2_en)
dat2 <= {i_rs2, dat2[7:1]};
if (dat3_en)
dat3 <= {i_rs2, dat3[7:1]};
if (dat_en)
dat <= {i_rs2, dat[31:1]};
if (i_wb_ack)
{dat3,dat2,dat1,dat0} <= i_wb_rdt;
dat <= i_wb_rdt;
if (dat_valid)
signbit <= dat_cur;

1
rtl/serv_top.v
View File

@@ -381,7 +381,6 @@ module serv_top
(
.i_clk (clk),
.i_en (cnt_en),
.i_init (init),
.i_mem_op (mem_op),
.i_signed (mem_signed),
.i_word (mem_word),