diff --git a/data/cmod_a7_35t.xdc b/data/cmod_a7_35t.xdc
new file mode 100644
index 0000000..1b49f7a
--- /dev/null
+++ b/data/cmod_a7_35t.xdc
@@ -0,0 +1,14 @@
+## 12 MHz Clock Signal
+set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { i_clk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
+create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports { i_clk }];
+
+## LEDs
+set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L12N_T1_MRCC_16 Sch=led[1]
+#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
+
+## UART
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { q }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { q  }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
diff --git a/servant.core b/servant.core
index c83919b..6e855af 100644
--- a/servant.core
+++ b/servant.core
@@ -72,6 +72,13 @@ filesets:
       - servant/servix_clock_gen.v : {file_type : verilogSource}
       - servant/servix.v : {file_type : verilogSource}
       - data/nexys_a7.xdc : {file_type : xdc}
+
+  cmod_a7_35t:
+    files:
+      - servant/servix_clock_gen.v : {file_type : verilogSource}
+      - servant/servix.v : {file_type : verilogSource}
+      - data/cmod_a7_35t.xdc : {file_type : xdc}
+
   arty_a7_35t:
     files:
       - servant/servix_clock_gen.v : {file_type : verilogSource}
@@ -213,6 +220,14 @@ targets:
       vivado: {part : xc7a100tcsg324-1}
     toplevel : servix
 
+  cmod_a7_35t:
+    default_tool: vivado
+    filesets : [mem_files, soc, cmod_a7_35t]
+    parameters : [memfile=blinky.hex, memsize, frequency=12]
+    tools:
+      vivado: {part : xc7a35tcpg236-1}
+    toplevel : servix
+
   arty_a7_35t:
     default_tool: vivado
     filesets : [mem_files, soc, arty_a7_35t]