CAPI=2:

name : ::serv:0

filesets:
  core:
    files:
      - rtl/serv_params.vh : {is_include_file : true}
      - rtl/shift_reg.v
      - rtl/ser_add.v
      - rtl/ser_eq.v
      - rtl/ser_lt.v
      - rtl/ser_shift.v
      - rtl/serv_alu.v
      - rtl/serv_csr.v
      - rtl/serv_ctrl.v
      - rtl/serv_decode.v
      - rtl/serv_mem_if.v
      - rtl/serv_regfile.v
      - rtl/serv_top.v
    file_type : verilogSource

  mem_files:
    files:
      - bitbang.hex  : {copyto : bitbang.hex}
      - hellomin.hex : {copyto : hellomin.hex}
    file_type : user
      
  pcf:
    files:
      - data/dummy.pcf : {file_type : PCF}
  serv_top_tb:
    files:
      - bench/serv_top_tb.v
    file_type : verilogSource
    depend : [vlog_tb_utils, "yosys:techlibs:ice40"]

  techlib:
    depend : ["yosys:techlibs:ice40fork"]
  wrapper:
    files:
      - testhalt.v
      - testprint.v
      - rtl/riscv_timer.v
      - rtl/wb_gpio.v
      - bench/serv_wrapper.v
    file_type : verilogSource
    depend : [wb_intercon, wb_ram]

  netlist:
    files: [synth.v : {file_type : verilogSource}]

  tinyfpga_bx:
    files:
      - data/tinyfpga_bx.pcf : {file_type : PCF}

  verilator_tb:
    files:
      - bench/serv_soc_tb.cpp : {file_type : verilogSource}
    depend : ["yosys:techlibs:ice40"]

targets:
  default:
    filesets : [core]
    toplevel : serv_top_tb

  synth:
    default_tool : icestorm
    filesets : [core, mem_files, wrapper, pcf]
    generate : [wb_intercon]
    toplevel : serv_wrapper

  tinyfpga_bx:
    default_tool : icestorm
    filesets : [core, mem_files, wrapper, tinyfpga_bx]
    generate : [wb_intercon]
    tools:
      icestorm:
        nextpnr_options : [--lp8k, --package, cm81, --freq, 16]
        pnr: next
    toplevel : serv_wrapper

  lint:
    default_tool : verilator
    filesets : [core, techlib]
    tools:
      verilator:
        mode : lint-only
    toplevel : serv_top

  serv_top_tb:
    default_tool: icarus
    filesets : [core, wrapper, serv_top_tb]
    generate : [wb_intercon]
    parameters : [RISCV_FORMAL=true, firmware]
    toplevel : serv_top_tb

  synth_tb:
    default_tool: icarus
    filesets : [netlist, serv_top_tb]
    toplevel : serv_top_tb

  verilator_tb:
    default_tool: verilator
    filesets : [core, wrapper, verilator_tb]
    generate : [wb_intercon]
    parameters : [RISCV_FORMAL=true, firmware, signature, uart_baudrate, vcd]
    tools:
      verilator:
        verilator_options : [-Wno-fatal, --trace]
    toplevel : serv_wrapper

parameters:
  RISCV_FORMAL:
    datatype  : bool
    paramtype : vlogdefine

  firmware:
    datatype : file
    paramtype : plusarg

  signature:
    datatype : file
    paramtype : plusarg
  uart_baudrate:
    datatype : int
    description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding)
    paramtype : plusarg

  vcd:
    datatype : bool
    paramtype : plusarg

generate:
  wb_intercon:
    generator: wb_intercon_gen
    parameters:
      masters:
        cpu_ibus:
          slaves : [mem]
        cpu_dbus:
          slaves : [mem, testprint, testhalt, gpio, timer]
      slaves:
        mem:
          offset : 0x00000000
          size   : 65536
        testprint:
          offset : 0x10000000
          size   : 4
        testhalt:
          offset : 0x20000000
          size   : 4
        gpio:
          offset : 0x30000000
          size   : 4
        timer:
          offset : 0xf00fff40
          size   : 16