CAPI=2:

name : ::serv:0

filesets:
  core:
    files:
      - rtl/serv_params.vh : {is_include_file : true}
      - rtl/shift_reg.v
      - rtl/ser_add.v
      - rtl/ser_lt.v
      - rtl/ser_shift.v
      - rtl/serv_bufreg.v
      - rtl/serv_alu.v
      - rtl/serv_csr.v
      - rtl/serv_ctrl.v
      - rtl/serv_decode.v
      - rtl/serv_mem_if.v
      - rtl/serv_regfile.v
      - rtl/serv_top.v
    file_type : verilogSource

  ice40_pll:
    files:
      - rtl/ice40_pll.v : {file_type : verilogSource}
    depend : ["fusesoc:utils:generators"]

  mem_files:
    files:
      - sw/blinky.hex       : {copyto : blinky.hex}
      - sw/zephyr_hello.hex : {copyto : zephyr_hello.hex}
    file_type : user

  serv_top_tb:
    files:
      - bench/serv_top_tb.v
    file_type : verilogSource
    depend : [vlog_tb_utils]

  wrapper:
    files:
      - rtl/serv_clock_gen.v
      - rtl/riscv_timer.v
      - rtl/wb_gpio.v
      - bench/serv_arbiter.v
      - bench/serv_mux.v
      - bench/serv_wrapper.v
    file_type : verilogSource
    depend : [wb_ram]

  netlist:
    files: [synth.v : {file_type : verilogSource}]

  tinyfpga_bx:
    files:
      - data/tinyfpga_bx.pcf : {file_type : PCF}

  icebreaker:
    files:
      - data/icebreaker.pcf : {file_type : PCF}

  verilator_tb:
    files:
      - bench/serv_soc_tb.cpp : {file_type : cppSource}

targets:
  default:
    filesets : [core]

  icebreaker:
    default_tool : icestorm
    filesets : [core, ice40_pll, mem_files, wrapper, icebreaker]
    generate: [icebreaker_pll]
    parameters : [memfile, memsize, PLL=ICE40_PAD]
    tools:
      icestorm:
        nextpnr_options: [--up5k, --freq, 16]
        pnr: next
    toplevel : serv_wrapper

  synth:
    default_tool : icestorm
    filesets : [core, mem_files, wrapper, tinyfpga_bx]
    toplevel : serv_wrapper

  tinyfpga_bx:
    default_tool : icestorm
    filesets : [core, ice40_pll, mem_files, wrapper, tinyfpga_bx]
    generate: [tinyfpga_bx_pll]
    parameters : [memfile, memsize, PLL=ICE40_CORE]
    tools:
      icestorm:
        nextpnr_options : [--lp8k, --package, cm81, --freq, 32]
        pnr: next
    toplevel : serv_wrapper

  lint:
    default_tool : verilator
    filesets : [core]
    tools:
      verilator:
        mode : lint-only
    toplevel : serv_top

  serv_top_tb:
    default_tool: icarus
    filesets : [core, wrapper, serv_top_tb]
    parameters : [RISCV_FORMAL=true, firmware]
    toplevel : serv_top_tb

  synth_tb:
    default_tool: icarus
    filesets : [netlist, serv_top_tb]
    toplevel : serv_top_tb

  verilator_tb:
    default_tool: verilator
    filesets : [core, wrapper, verilator_tb]
    parameters : [RISCV_FORMAL, firmware, memsize, signature, uart_baudrate, vcd]
    tools:
      verilator:
        verilator_options : [-Wno-fatal, --trace]
    toplevel : serv_wrapper

parameters:
  PLL:
    datatype : str
    description : PLL type to use for main clock generation
    paramtype : vlogparam

  RISCV_FORMAL:
    datatype  : bool
    paramtype : vlogdefine

  firmware:
    datatype : file
    description : Preload RAM with a hex file at runtime (overrides memfile)
    paramtype : plusarg

  memfile:
    datatype    : file
    description : Preload RAM with a hex file at compile-time
    paramtype   : vlogparam

  memsize:
    datatype    : int
    default     : 8192
    description : Memory size in bytes for RAM (default 8kiB)
    paramtype   : vlogparam

  signature:
    datatype : file
    paramtype : plusarg
  uart_baudrate:
    datatype : int
    description : Treat q output as an UART with the specified baudrate (0 or omitted parameter disables UART decoding)
    paramtype : plusarg

  vcd:
    datatype : bool
    paramtype : plusarg

generate:
  icebreaker_pll:
    generator: icepll
    parameters:
      freq_out : 16

  tinyfpga_bx_pll:
    generator: icepll
    parameters:
      freq_in  : 16
      freq_out : 32