mirror of
https://github.com/olofk/serv.git
synced 2026-01-11 23:42:50 +00:00
3b9331b3b5
fusesoc core show servant CORE INFO Name: ::servant:1.2.1 Description: <No description> Core root: fusesoc_libraries/serv Core file: servant.core Targets: alchitry_au : Open-hardware Alchitry AU FPGA board Creating bitstream... Writing bitstream ./servix.bit... Writing bitstream ./servix.bin... Bitstream generation completed INFO: [Common 17-206] Exiting Vivado at Fri Jun 14 16:49:54 2024... Resources used fusesoc run --target=alchitry_au servant --uart_baudrate=57600 --memfile ./fusesoc_libraries/serv/sw/zephyr_hello.hex +----------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +----------------------------+------+-------+------------+-----------+-------+ | Slice LUTs | 244 | 0 | 0 | 20800 | 1.17 | | LUT as Logic | 243 | 0 | 0 | 20800 | 1.17 | | LUT as Memory | 1 | 0 | 0 | 9600 | 0.01 | | LUT as Distributed RAM | 0 | 0 | | | | | LUT as Shift Register | 1 | 0 | | | | | Slice Registers | 238 | 0 | 0 | 41600 | 0.57 | | Register as Flip Flop | 238 | 0 | 0 | 41600 | 0.57 | | Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | | F7 Muxes | 3 | 0 | 0 | 16300 | 0.02 | | F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 | +----------------------------+------+-------+------------+-----------+-------+
17 lines
541 B
Tcl
17 lines
541 B
Tcl
## Clock signal
|
|
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports i_clk];
|
|
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk];
|
|
|
|
## Reset
|
|
set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS33 } [get_ports i_rst_n];
|
|
|
|
## LED
|
|
## set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports q];
|
|
|
|
## USB Serial output
|
|
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports q]
|
|
|
|
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
|
set_property CFGBVS VCCO [current_design]
|
|
|