mirror of
https://github.com/olofk/serv.git
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102 lines
2.6 KiB
Verilog
102 lines
2.6 KiB
Verilog
/*
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* serv_bufreg.v : SERV buffer register for load/store address and shift data
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*
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* SPDX-FileCopyrightText: 2019 Olof Kindgren <olof@award-winning.me>
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* SPDX-License-Identifier: ISC
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*/
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module serv_bufreg #(
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parameter [0:0] MDU = 0,
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parameter W = 1,
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parameter B = W-1
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)(
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input wire i_clk,
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//State
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input wire i_cnt0,
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input wire i_cnt1,
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input wire i_cnt_done,
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input wire i_en,
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input wire i_init,
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input wire i_mdu_op,
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output wire [1:0] o_lsb,
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//Control
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input wire i_rs1_en,
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input wire i_imm_en,
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input wire i_clr_lsb,
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input wire i_shift_op,
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input wire i_right_shift_op,
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input wire [2:0] i_shamt,
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input wire i_sh_signed,
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//Data
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input wire [B:0] i_rs1,
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input wire [B:0] i_imm,
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output wire [B:0] o_q,
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//External
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output wire [31:0] o_dbus_adr,
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//Extension
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output wire [31:0] o_ext_rs1);
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wire c;
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wire [B:0] q;
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reg [B:0] c_r;
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reg [31:0] data;
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wire [B:0] clr_lsb;
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assign clr_lsb[0] = i_cnt0 & i_clr_lsb;
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generate
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if (W > 1) begin : gen_clr_lsb_w_gt_1
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assign clr_lsb[B:1] = {B{1'b0}};
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end
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endgenerate
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assign {c,q} = {1'b0,(i_rs1 & {W{i_rs1_en}})} + {1'b0,(i_imm & {W{i_imm_en}} & ~clr_lsb)} + c_r;
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always @(posedge i_clk) begin
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//Make sure carry is cleared before loading new data
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c_r <= {W{1'b0}};
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c_r[0] <= c & i_en;
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end
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generate
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if (W == 1) begin : gen_w_eq_1
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always @(posedge i_clk) begin
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if (i_en)
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data[31:2] <= {i_init ? q : {W{data[31] & i_sh_signed}}, data[31:3]};
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if (i_init ? (i_cnt0 | i_cnt1) : i_en)
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data[1:0] <= {i_init ? q : data[2], data[1]};
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end
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assign o_lsb = (MDU & i_mdu_op) ? 2'b00 : data[1:0];
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assign o_q = data[0] & {W{i_en}};
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end else if (W == 4) begin : gen_lsb_w_4
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reg [1:0] lsb;
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reg [W-2:0] data_tail;
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wire [2:0] shift_amount
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= !i_shift_op ? 3'd3 :
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i_right_shift_op ? (3'd3+{1'b0,i_shamt[1:0]}) :
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({1'b0,~i_shamt[1:0]});
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always @(posedge i_clk) begin
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if (i_en)
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if (i_cnt0) lsb <= q[1:0];
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if (i_en)
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data <= {i_init ? q : {W{i_sh_signed & data[31]}}, data[31:W]};
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if (i_en)
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data_tail <= data[B:1] & {B{~i_cnt_done}};
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end
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wire [2*W+B-2:0] muxdata = {data[W+B-1:0],data_tail};
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wire [B:0] muxout = muxdata[{1'b0,shift_amount}+:W];
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assign o_lsb = (MDU & i_mdu_op) ? 2'b00 : lsb;
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assign o_q = i_en ? muxout : {W{1'b0}};
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end
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endgenerate
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assign o_dbus_adr = {data[31:2], 2'b00};
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assign o_ext_rs1 = data;
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endmodule
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