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47 lines
893 B
Verilog
47 lines
893 B
Verilog
// based on servant_upduino2.v
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`default_nettype none
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module servant_md_kolibri
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(
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input wire clk48,
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output wire led,
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output wire tx);
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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wire clk32;
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wire locked;
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reg rst = 1'b1;
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// 48MHz -> 32MHz
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0010), // DIVR = 2
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.DIVF(7'b0111111), // DIVF = 63
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.DIVQ(3'b101), // DIVQ = 5
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) uut (
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.LOCK(locked),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(clk48),
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.PLLOUTCORE(clk32)
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);
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always @(posedge clk32)
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rst <= !locked;
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servant
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#(.memfile (memfile),
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.memsize (memsize))
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servant
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(.wb_clk (clk32),
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.wb_rst (rst),
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.q (tx));
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assign led = tx;
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endmodule
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