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52 lines
1.2 KiB
Verilog
52 lines
1.2 KiB
Verilog
/*
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mem = 00
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gpio = 01
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timer = 10
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testcon = 11
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*/
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module servant_mux
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(
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input wire i_clk,
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input wire i_rst,
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input wire [31:0] i_wb_cpu_adr,
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input wire [31:0] i_wb_cpu_dat,
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input wire [3:0] i_wb_cpu_sel,
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input wire i_wb_cpu_we,
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input wire i_wb_cpu_cyc,
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output wire [31:0] o_wb_cpu_rdt,
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output reg o_wb_cpu_ack,
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output wire o_wb_gpio_dat,
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output wire o_wb_gpio_we,
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output wire o_wb_gpio_cyc,
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input wire i_wb_gpio_rdt,
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output wire [31:0] o_wb_timer_dat,
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output wire o_wb_timer_we,
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output wire o_wb_timer_cyc,
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input wire [31:0] i_wb_timer_rdt);
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parameter sim = 0;
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wire [1:0] s = i_wb_cpu_adr[31:30];
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assign o_wb_cpu_rdt = s[1] ? i_wb_timer_rdt : {31'd0,i_wb_gpio_rdt};
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always @(posedge i_clk) begin
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o_wb_cpu_ack <= 1'b0;
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if (i_wb_cpu_cyc & !o_wb_cpu_ack)
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o_wb_cpu_ack <= 1'b1;
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if (i_rst)
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o_wb_cpu_ack <= 1'b0;
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end
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assign o_wb_gpio_dat = i_wb_cpu_dat[0];
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assign o_wb_gpio_we = i_wb_cpu_we;
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assign o_wb_gpio_cyc = i_wb_cpu_cyc & !s[1];
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assign o_wb_timer_dat = i_wb_cpu_dat;
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assign o_wb_timer_we = i_wb_cpu_we;
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assign o_wb_timer_cyc = i_wb_cpu_cyc & s[1];
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endmodule
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