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67 lines
1.1 KiB
Verilog
67 lines
1.1 KiB
Verilog
`default_nettype none
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module servant_pf (
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input wire i_clk,
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input wire resetb,
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output wire o_led1,
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output wire o_led2,
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output wire o_led3 = 1'b0,
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output wire o_led4 = 1'b0,
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output wire o_led5 = 1'b0,
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output wire o_led6 = 1'b0,
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output wire o_led7 = 1'b0,
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output wire o_led8 = 1'b0,
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output wire o_uart_tx);
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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wire clk;
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wire rst;
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wire q;
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wire CLKINT_0_Y;
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reg heartbeat;
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CLKINT CLKINT_0(
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.A (i_clk),
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.Y (CLKINT_0_Y)
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);
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servant_pf_clock_gen #(
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.refclk(50),
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.frequency(32)
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) clock_gen (
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.i_clk (CLKINT_0_Y),
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.o_clk (clk)
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);
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servant #(
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.memfile (memfile),
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.memsize (memsize)
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) servant (
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.wb_clk (clk),
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.wb_rst (rst),
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.q (q)
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);
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// heartbeat LED
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reg [$clog2(32000000)-1:0] count = 0;
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always @(posedge clk) begin
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if (rst) begin
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count <= 0;
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heartbeat <= 0;
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end else
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count <= count + 1;
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if (count == 32000000-1) begin
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heartbeat <= !heartbeat;
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count <= 0;
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end
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end
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assign rst = ~resetb;
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assign o_led1 = q;
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assign o_led2 = heartbeat;
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assign o_uart_tx = q;
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endmodule
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