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https://github.com/olofk/serv.git
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158 lines
4.0 KiB
Verilog
158 lines
4.0 KiB
Verilog
`timescale 1 ns/100 ps
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module servant_pf_clock_gen(
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input wire i_clk,
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output wire o_clk,
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output reg o_lock);
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// for documentation
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parameter refclk = 50;
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parameter frequency = 32;
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// PLL in internal Post-VCO Feedback mode
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localparam [11:0] fbdiv = 12'b100111000000; // 2496
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localparam [5:0] rfdiv = 6'b011001; // 25;
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localparam vco = 4992; // refclk * fbdiv / rfdiv;
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localparam [6:0] odiv = 7'b0100111; // vco / (4 * frequency);
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wire gnd_net, vcc_net, pll_inst_0_clkint_0;
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wire nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11, nc12,
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nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, nc23,
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nc24, nc25, nc26, nc27, nc28, nc29, nc30, nc31, nc32, nc33, nc34,
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nc35, nc36, nc37, nc38, nc39, nc40;
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VCC vcc_inst (.Y(vcc_net));
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GND gnd_inst (.Y(gnd_net));
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PLL #(
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.VCOFREQUENCY(vco),
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.DELAY_LINE_SIMULATION_MODE(""),
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.DATA_RATE(0.0),
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.FORMAL_NAME(""),
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.INTERFACE_NAME(""),
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.INTERFACE_LEVEL(3'b0),
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.SOFTRESET(1'b0),
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.SOFT_POWERDOWN_N(1'b1),
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.RFDIV_EN(1'b1),
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.OUT0_DIV_EN(1'b1),
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.OUT1_DIV_EN(1'b0),
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.OUT2_DIV_EN(1'b0),
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.OUT3_DIV_EN(1'b0),
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.SOFT_REF_CLK_SEL(1'b0),
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.RESET_ON_LOCK(1'b1),
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.BYPASS_CLK_SEL(4'b0),
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.BYPASS_GO_EN_N(1'b1),
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.BYPASS_PLL(4'b0),
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.BYPASS_OUT_DIVIDER(4'b0),
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.FF_REQUIRES_LOCK(1'b0),
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.FSE_N(1'b0),
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.FB_CLK_SEL_0(2'b00),
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.FB_CLK_SEL_1(1'b0),
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.RFDIV(rfdiv),
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.FRAC_EN(1'b0),
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.FRAC_DAC_EN(1'b0),
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.DIV0_RST_DELAY(3'b000),
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.DIV0_VAL(odiv),
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.DIV1_RST_DELAY(3'b0),
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.DIV1_VAL(7'b1),
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.DIV2_RST_DELAY(3'b0),
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.DIV2_VAL(7'b1),
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.DIV3_RST_DELAY(3'b0),
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.DIV3_VAL(7'b1),
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.DIV3_CLK_SEL(1'b0),
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.BW_INT_CTRL(2'b0),
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.BW_PROP_CTRL(2'b01),
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.IREF_EN(1'b1),
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.IREF_TOGGLE(1'b0),
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.LOCK_CNT(4'b1000),
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.DESKEW_CAL_CNT(3'b110),
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.DESKEW_CAL_EN(1'b1),
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.DESKEW_CAL_BYPASS(1'b0),
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.SYNC_REF_DIV_EN(1'b0),
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.SYNC_REF_DIV_EN_2(1'b0),
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.OUT0_PHASE_SEL(3'b000),
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.OUT1_PHASE_SEL(3'b0),
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.OUT2_PHASE_SEL(3'b0),
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.OUT3_PHASE_SEL(3'b0),
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.SOFT_LOAD_PHASE_N(1'b1),
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.SSM_DIV_VAL(6'b1),
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.FB_FRAC_VAL(24'b0),
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.SSM_SPREAD_MODE(1'b0),
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.SSM_MODULATION(5'b00101),
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.FB_INT_VAL(fbdiv),
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.SSM_EN_N(1'b1),
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.SSM_EXT_WAVE_EN(2'b0),
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.SSM_EXT_WAVE_MAX_ADDR(8'b0),
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.SSM_RANDOM_EN(1'b0),
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.SSM_RANDOM_PATTERN_SEL(3'b0),
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.CDMUX0_SEL(2'b0),
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.CDMUX1_SEL(1'b1),
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.CDMUX2_SEL(1'b0),
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.CDELAY0_SEL(8'b0),
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.CDELAY0_EN(1'b0),
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.DRI_EN(1'b1)
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) pll_inst_0 (
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.LOCK(o_lock),
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.SSCG_WAVE_TABLE_ADDR({
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nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7
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}),
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.DELAY_LINE_OUT_OF_RANGE(),
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.POWERDOWN_N(vcc_net),
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.OUT0_EN(vcc_net),
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.OUT1_EN(gnd_net),
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.OUT2_EN(gnd_net),
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.OUT3_EN(gnd_net),
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.REF_CLK_SEL(gnd_net),
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.BYPASS_EN_N(vcc_net),
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.LOAD_PHASE_N(vcc_net),
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.SSCG_WAVE_TABLE({
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net
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}),
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.PHASE_DIRECTION(gnd_net),
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.PHASE_ROTATE(gnd_net),
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.PHASE_OUT0_SEL(gnd_net),
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.PHASE_OUT1_SEL(gnd_net),
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.PHASE_OUT2_SEL(gnd_net),
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.PHASE_OUT3_SEL(gnd_net),
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.DELAY_LINE_MOVE(gnd_net),
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.DELAY_LINE_DIRECTION(gnd_net),
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.DELAY_LINE_WIDE(gnd_net),
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.DELAY_LINE_LOAD(vcc_net),
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.REFCLK_SYNC_EN(gnd_net),
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.REF_CLK_0(i_clk),
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.REF_CLK_1(gnd_net),
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.FB_CLK(gnd_net),
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.OUT0(pll_inst_0_clkint_0),
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.OUT1(),
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.OUT2(),
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.OUT3(),
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.DRI_CLK(gnd_net),
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.DRI_CTRL({
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net
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}),
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.DRI_WDATA({
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
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gnd_net, gnd_net, gnd_net, gnd_net, gnd_net
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}),
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.DRI_ARST_N(vcc_net),
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.DRI_RDATA({
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nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18,
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nc19, nc20, nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29,
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nc30, nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39,
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nc40
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}),
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.DRI_INTERRUPT()
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);
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CLKINT clkint_0 (
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.A(pll_inst_0_clkint_0),
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.Y(o_clk)
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);
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endmodule
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