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35 lines
755 B
Verilog
35 lines
755 B
Verilog
`default_nettype none
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module service_go_board
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(input wire i_clk,
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output wire o_led1,
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output wire o_led2 = 1'b0,
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output wire o_led3 = 1'b0,
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output wire o_led4 = 1'b0,
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output wire o_uart_tx);
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parameter memfile = "blinky.hex";
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parameter memsize = 512;
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// Assert reset for 64 clock cycles. Use the 7th bit as the reset signal.
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reg [6:0] rst_count;
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wire rst_r = !rst_count[6];
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always @(posedge i_clk) begin
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if (rst_r == 1) begin
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rst_count <= rst_count + 1;
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end
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end
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wire q;
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servant
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#(.memfile (memfile),
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.memsize (memsize))
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servant
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(.wb_clk (i_clk),
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.wb_rst (rst_r),
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.q (q));
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assign o_led1 = q;
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assign o_uart_tx = q;
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endmodule
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