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8d91e2d288
Servile is a new convenience wrapper that implements common common configuration for SERV-based systems so that they don't have to be repeated in every design.
46 lines
1.5 KiB
Verilog
46 lines
1.5 KiB
Verilog
/*
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* servile_arbiter.v : I/D arbiter for the servile convenience wrapper.
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* Relies on the fact that not ibus and dbus are active at the same time.
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*
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* SPDX-FileCopyrightText: 2024 Olof Kindgren <olof.kindgren@gmail.com>
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* SPDX-License-Identifier: Apache-2.0
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*/
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module servile_arbiter
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(
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input wire [31:0] i_wb_cpu_dbus_adr,
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input wire [31:0] i_wb_cpu_dbus_dat,
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input wire [3:0] i_wb_cpu_dbus_sel,
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input wire i_wb_cpu_dbus_we,
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input wire i_wb_cpu_dbus_stb,
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output wire [31:0] o_wb_cpu_dbus_rdt,
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output wire o_wb_cpu_dbus_ack,
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input wire [31:0] i_wb_cpu_ibus_adr,
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input wire i_wb_cpu_ibus_stb,
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output wire [31:0] o_wb_cpu_ibus_rdt,
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output wire o_wb_cpu_ibus_ack,
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output wire [31:0] o_wb_mem_adr,
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output wire [31:0] o_wb_mem_dat,
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output wire [3:0] o_wb_mem_sel,
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output wire o_wb_mem_we,
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output wire o_wb_mem_stb,
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input wire [31:0] i_wb_mem_rdt,
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input wire i_wb_mem_ack);
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assign o_wb_cpu_dbus_rdt = i_wb_mem_rdt;
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assign o_wb_cpu_dbus_ack = i_wb_mem_ack & !i_wb_cpu_ibus_stb;
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assign o_wb_cpu_ibus_rdt = i_wb_mem_rdt;
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assign o_wb_cpu_ibus_ack = i_wb_mem_ack & i_wb_cpu_ibus_stb;
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assign o_wb_mem_adr = i_wb_cpu_ibus_stb ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr;
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assign o_wb_mem_dat = i_wb_cpu_dbus_dat;
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assign o_wb_mem_sel = i_wb_cpu_dbus_sel;
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assign o_wb_mem_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_stb;
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assign o_wb_mem_stb = i_wb_cpu_ibus_stb | i_wb_cpu_dbus_stb;
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endmodule
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