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8d91e2d288
Servile is a new convenience wrapper that implements common common configuration for SERV-based systems so that they don't have to be repeated in every design.
78 lines
2.3 KiB
Verilog
78 lines
2.3 KiB
Verilog
/*
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* servile_rf_mem_if.v : Arbiter to allow a shared SRAM for RF and memory accesses. RF is mapped to the highest 128 bytes of the memory. Requires 8-bit RF accesses.
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*
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* SPDX-FileCopyrightText: 2024 Olof Kindgren <olof.kindgren@gmail.com>
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* SPDX-License-Identifier: Apache-2.0
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*/
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`default_nettype none
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module servile_rf_mem_if
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#(//Memory parameters
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parameter depth = 256,
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//RF parameters
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parameter rf_regs = 32,
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//Internally calculated. Do not touch
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parameter rf_depth = $clog2(rf_regs*4),
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parameter aw = $clog2(depth))
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(
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input wire i_clk,
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input wire i_rst,
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input wire [rf_depth-1:0] i_waddr,
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input wire [7:0] i_wdata,
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input wire i_wen,
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input wire [rf_depth-1:0] i_raddr,
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output wire [7:0] o_rdata,
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input wire i_ren,
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output wire [aw-1:0] o_sram_waddr,
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output wire [7:0] o_sram_wdata,
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output wire o_sram_wen,
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output wire [aw-1:0] o_sram_raddr,
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input wire [7:0] i_sram_rdata,
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output wire o_sram_ren,
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input wire [aw-1:2] i_wb_adr,
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input wire [31:0] i_wb_dat,
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input wire [3:0] i_wb_sel,
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input wire i_wb_we,
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input wire i_wb_stb,
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output wire [31:0] o_wb_rdt,
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output reg o_wb_ack);
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reg [1:0] bsel;
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wire wb_en = i_wb_stb & !i_wen & !o_wb_ack;
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wire wb_we = i_wb_we & i_wb_sel[bsel];
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wire [aw-1:0] rf_waddr = ~{{aw-rf_depth{1'b0}},i_waddr};
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wire [aw-1:0] rf_raddr = ~{{aw-rf_depth{1'b0}},i_raddr};
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assign o_sram_waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : rf_waddr;
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assign o_sram_wdata = wb_en ? i_wb_dat[bsel*8+:8] : i_wdata;
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assign o_sram_wen = wb_en ? wb_we : i_wen;
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assign o_sram_raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : rf_raddr;
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assign o_sram_ren = wb_en ? !i_wb_we : i_ren;
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reg [23:0] wb_rdt;
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assign o_wb_rdt = {i_sram_rdata, wb_rdt};
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reg regzero;
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always @(posedge i_clk) begin
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if (wb_en) bsel <= bsel + 2'd1;
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o_wb_ack <= wb_en & &bsel;
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if (bsel == 2'b01) wb_rdt[7:0] <= i_sram_rdata;
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if (bsel == 2'b10) wb_rdt[15:8] <= i_sram_rdata;
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if (bsel == 2'b11) wb_rdt[23:16] <= i_sram_rdata;
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if (i_rst) begin
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bsel <= 2'd0;
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o_wb_ack <= 1'b0;
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end
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regzero <= &i_raddr[rf_depth-1:2];
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end
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assign o_rdata = regzero ? 8'd0 : i_sram_rdata;
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endmodule
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