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43 lines
812 B
Verilog
43 lines
812 B
Verilog
module servant_qf
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(
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input wire i_rst_n,
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output wire o_uart_tx);
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reg rst_r;
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wire i_clk;
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wire i_rst;
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wire clk;
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// wire rst;
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// parameter memfile = "zephyr_hello.hex";
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parameter memfile = "blinky.hex";
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parameter memsize = 2048;
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qlal4s3b_cell_macro u_qlal4s3b_cell_macro
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(
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.Sys_Clk0 (i_clk),
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.Sys_Clk0_Rst (i_rst),
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.Sys_Clk1 (),
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.Sys_Clk1_Rst ());
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gclkbuff u_gclkbuff_clock0 (.A(i_clk), .Z(clk));
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// gclkbuff u_gclkbuff_reset0 (.A(i_rst), .Z(rst));
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wire o_uart_tx = q;
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reg rst;
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always @(posedge clk)
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rst <= !i_rst_n;
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servant
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#(.memfile (memfile),
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.memsize (memsize))
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servant
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(.wb_clk (clk),
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.wb_rst (rst),
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.q (q));
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endmodule
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