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58 lines
1.0 KiB
Verilog
58 lines
1.0 KiB
Verilog
`default_nettype none
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module servant_nexys_a7_clock_gen
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(input wire i_clk,
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input wire i_rst,
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input wire i_clk0_en,
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input wire i_clk1_en,
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output wire o_clk0,
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output wire o_clk1,
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output reg o_rst);
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wire clkfb;
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wire locked;
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wire pll_rst;
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wire pll_clk;
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reg locked_r;
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assign pll_rst = !i_rst;
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MMCME2_BASE
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#(.CLKIN1_PERIOD (10), //100MHz
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/* Set VCO frequency to 100*8.0=800 MHz
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Allowed values are 2.0 to 64.0. Resulting VCO freq
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needs to be 600-1200MHz */
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.CLKFBOUT_MULT_F (6.000),
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.CLKOUT0_DIVIDE_F (64.000)) // 800/25 = 32 MHz
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pll
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(.CLKIN1 (i_clk),
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.RST (pll_rst),
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.CLKOUT0 (pll_clk),
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.LOCKED (locked),
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.CLKFBOUT (clkfb),
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.CLKFBIN (clkfb));
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always @(posedge pll_clk) begin
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locked_r <= locked;
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o_rst <= !locked_r;
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end
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BUFGCE clk0_buf
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(
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.I (pll_clk),
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.O (o_clk0),
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.CE (i_clk0_en));
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BUFGCE clk1_buf
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(
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.I (pll_clk),
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.O (o_clk1),
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.CE (i_clk1_en));
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endmodule
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`default_nettype wire
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