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47 lines
858 B
Verilog
47 lines
858 B
Verilog
`default_nettype none
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module servant_xyloni
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(
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input wire i_clk,
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input wire i_pll_locked,
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input wire i_rst,
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output wire o_uart_tx,
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output wire l2,
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output wire l3,
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output wire l4,
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output wire q);
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assign l4 = i_pll_locked;
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assign l3 = i_rst;
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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wire wb_clk;
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wire wb_rst;
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reg [3:0] rstreg = 4'b1111;
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always @(posedge i_clk) begin
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if (i_pll_locked) rstreg <= {rstreg[2:0],~i_rst};
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else rstreg <= 4'b1111;
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end
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assign o_uart_tx = q;
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assign wb_clk = i_clk;
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assign wb_rst = i_rst;
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reg [27:0] cnt = 28'd0;
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always @(posedge i_clk) cnt <= cnt + 28'd1;
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assign l2 = cnt[21];
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servant
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#(.memfile (memfile),
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.memsize (memsize))
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servant
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(.wb_clk (wb_clk),
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.wb_rst (wb_rst),
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.q (q));
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endmodule
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