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45 lines
1.2 KiB
Verilog
45 lines
1.2 KiB
Verilog
`default_nettype none
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module serv_immdec
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(
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input wire i_clk,
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//Input
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input wire i_cnt_en,
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input wire i_csr_imm_en,
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output wire o_csr_imm,
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input wire [31:2] i_wb_rdt,
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input wire i_wb_en,
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input wire i_cnt_done,
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input wire [3:0] i_ctrl,
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output wire o_imm);
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reg signbit;
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reg [8:0] imm19_12_20;
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reg imm7;
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reg [5:0] imm30_25;
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reg [4:0] imm24_20;
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reg [4:0] imm11_7;
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assign o_imm = i_cnt_done ? signbit : i_ctrl[0] ? imm11_7[0] : imm24_20[0];
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assign o_csr_imm = imm19_12_20[4];
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always @(posedge i_clk) begin
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if (i_wb_en) begin
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signbit <= i_wb_rdt[31] & !i_csr_imm_en;
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imm19_12_20 <= {i_wb_rdt[19:12],i_wb_rdt[20]};
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imm7 <= i_wb_rdt[7];
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imm30_25 <= i_wb_rdt[30:25];
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imm24_20 <= i_wb_rdt[24:20];
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imm11_7 <= i_wb_rdt[11:7];
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end
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if (i_cnt_en) begin
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imm19_12_20 <= {i_ctrl[3] ? signbit : imm24_20[0], imm19_12_20[8:1]};
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imm7 <= signbit;
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imm30_25 <= {i_ctrl[2] ? imm7 : i_ctrl[1] ? signbit : imm19_12_20[0], imm30_25[5:1]};
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imm24_20 <= {imm30_25[0], imm24_20[4:1]};
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imm11_7 <= {imm30_25[0], imm11_7[4:1]};
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end
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end
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endmodule
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