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63 lines
1.2 KiB
Verilog
63 lines
1.2 KiB
Verilog
`default_nettype none
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module servant_ac701
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(
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input wire sys_clk_p,
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input wire sys_clk_n,
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input wire btn,
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output wire q);
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parameter frequency = 16;
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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parameter PLL = "NONE";
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wire wb_clk;
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reg wb_rst;
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wire clk;
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wire clkfb;
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wire locked;
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reg locked_r;
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IBUFDS ibufds
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(
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.I (sys_clk_p),
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.IB (sys_clk_n),
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.O (clk)
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);
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PLLE2_BASE
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#(.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT(8),
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.CLKIN1_PERIOD(5.0), //200MHz
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.CLKOUT0_DIVIDE((frequency == 32) ? 50 : 100),
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.DIVCLK_DIVIDE(1),
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.STARTUP_WAIT("FALSE"))
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PLLE2_BASE_inst
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(.CLKOUT0(wb_clk),
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.CLKOUT1(),
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.CLKOUT2(),
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.CLKOUT3(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKFBOUT(clkfb),
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.LOCKED(locked),
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.CLKIN1(clk),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.CLKFBIN(clkfb));
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always @(posedge wb_clk) begin
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locked_r <= locked;
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wb_rst <= !locked_r;
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end
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servant
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#(.memfile (memfile),
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.memsize (memsize))
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servant
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(.wb_clk (wb_clk),
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.wb_rst (wb_rst),
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.q (q));
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endmodule
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