mirror of
https://github.com/olofk/serv.git
synced 2026-01-13 15:17:25 +00:00
116 lines
2.3 KiB
Plaintext
116 lines
2.3 KiB
Plaintext
CAPI=2:
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name : ::serv:0
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filesets:
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core:
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files:
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- rtl/serv_params.vh : {is_include_file : true}
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- rtl/shift_reg.v
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- rtl/ser_add.v
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- rtl/ser_eq.v
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- rtl/ser_lt.v
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- rtl/ser_shift.v
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- rtl/serv_alu.v
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- rtl/serv_csr.v
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- rtl/serv_ctrl.v
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- rtl/serv_decode.v
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- rtl/serv_mem_if.v
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- rtl/serv_regfile.v
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- rtl/serv_top.v
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file_type : verilogSource
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serv_top_tb:
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files:
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- bench/serv_top_tb.v
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file_type : verilogSource
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depend : [vlog_tb_utils, "yosys:techlibs:ice40"]
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wrapper:
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files:
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- testhalt.v
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- testprint.v
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- rtl/riscv_timer.v
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- bench/serv_wrapper.v
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file_type : verilogSource
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depend : [wb_intercon, wb_ram]
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pcf:
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files: [data/dummy.pcf : {file_type : PCF}]
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verilator_tb:
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files:
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- bench/serv_soc_tb.cpp : {file_type : verilogSource}
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depend : ["yosys:techlibs:ice40"]
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targets:
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default:
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filesets : [core]
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toplevel : serv_top_tb
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synth:
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default_tool : icestorm
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filesets : [core, pcf]
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toplevel : serv_top
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lint:
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default_tool : verilator
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filesets : [core]
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tools:
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verilator:
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mode : lint-only
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toplevel : serv_top
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serv_top_tb:
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default_tool: icarus
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filesets : [core, wrapper, serv_top_tb]
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generate : [wb_intercon]
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parameters : [RISCV_FORMAL=true, firmware]
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toplevel : serv_top_tb
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verilator_tb:
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default_tool: verilator
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filesets : [core, wrapper, verilator_tb]
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generate : [wb_intercon]
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parameters : [RISCV_FORMAL=true, firmware, signature]
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tools:
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verilator:
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verilator_options : [-Wno-fatal, --trace]
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toplevel : serv_wrapper
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parameters:
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RISCV_FORMAL:
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datatype : bool
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paramtype : vlogdefine
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firmware:
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datatype : file
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paramtype : plusarg
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signature:
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datatype : file
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paramtype : plusarg
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generate:
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wb_intercon:
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generator: wb_intercon_gen
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parameters:
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masters:
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cpu_ibus:
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slaves : [mem]
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cpu_dbus:
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slaves : [mem, testprint, testhalt, timer]
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slaves:
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mem:
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offset : 0x80000000
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size : 65536
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testprint:
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offset : 0x10000000
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size : 4
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testhalt:
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offset : 0x20000000
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size : 4
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timer:
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offset : 0xf00fff40
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size : 16
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