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olofk.serv/serv.core
2018-11-09 21:26:13 +01:00

111 lines
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CAPI=2:
name : ::serv:0
filesets:
core:
files:
- rtl/camd_ram.v
- rtl/serv_params.vh : {is_include_file : true}
- rtl/shift_reg.v
- rtl/ser_add.v
- rtl/ser_eq.v
- rtl/ser_lt.v
- rtl/ser_shift.v
- rtl/serv_alu.v
- rtl/serv_ctrl.v
- rtl/serv_decode.v
- rtl/serv_mem_if.v
- rtl/serv_regfile.v
- rtl/serv_top.v
file_type : verilogSource
depend : [wb_ram]
ser_add_tb:
files:
- ser_add_tb.v
file_type : verilogSource
depend : [vlog_tb_utils]
serv_ctrl_tb:
files:
- bench/serv_ctrl_tb.v : {file_type : verilogSource}
depend : [vlog_tb_utils]
serv_decode_tb:
files: [bench/serv_decode_tb.v : {file_type : verilogSource}]
depend : [vlog_tb_utils]
serv_top_tb:
files:
- firmware.hex : {copyto : firmware.hex, file_type : user}
- testprint.v
- bench/serv_top_tb.v
file_type : verilogSource
depend : [vlog_tb_utils, wb_intercon, "yosys:techlibs:ice40"]
pcf:
files: [data/dummy.pcf : {file_type : PCF}]
targets:
default:
filesets : [core]
toplevel : serv_top_tb
synth:
default_tool : icestorm
filesets : [core, pcf]
toplevel : serv_top
lint:
default_tool : verilator
filesets : [core]
tools:
verilator:
mode : lint-only
toplevel : serv_top
ser_add_tb:
default_tool : icarus
filesets: [core, ser_add_tb]
toplevel: ser_add_tb
serv_ctrl_tb:
default_tool: icarus
filesets : [core, serv_ctrl_tb]
toplevel : serv_ctrl_tb
serv_decode_tb:
default_tool: icarus
filesets : [core, serv_decode_tb]
toplevel : serv_decode_tb
serv_top_tb:
default_tool: icarus
filesets : [core, serv_top_tb]
generate : [wb_intercon]
parameters : [RISCV_FORMAL=true]
toplevel : serv_top_tb
parameters:
RISCV_FORMAL:
datatype : bool
paramtype : vlogdefine
generate:
wb_intercon:
generator: wb_intercon_gen
parameters:
masters:
cpu_ibus:
slaves : [mem]
cpu_dbus:
slaves : [mem, testprint, testpassed]
slaves:
mem:
offset : 0
size : 65536
testprint:
offset : 0x10000000
size : 4
testpassed:
offset : 0x20000000
size : 4