mirror of
https://github.com/olofk/serv.git
synced 2026-01-11 23:42:50 +00:00
165 lines
4.9 KiB
Verilog
165 lines
4.9 KiB
Verilog
module serv_state
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(
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input wire i_clk,
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input wire i_rst,
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input wire i_new_irq,
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output wire o_trap_taken,
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output reg o_pending_irq,
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input wire i_dbus_ack,
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input wire i_ibus_ack,
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output wire o_rf_rreq,
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output wire o_rf_wreq,
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input wire i_rf_ready,
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output wire o_rf_rd_en,
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input wire i_cond_branch,
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input wire i_bne_or_bge,
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input wire i_alu_cmp,
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input wire i_branch_op,
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input wire i_mem_op,
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input wire i_shift_op,
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input wire i_slt_op,
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input wire i_e_op,
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input wire i_rd_op,
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output reg o_init,
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output reg o_cnt_en,
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output wire o_cnt0,
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output wire o_cnt0to3,
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output wire o_cnt12to31,
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output wire o_cnt1,
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output wire o_cnt2,
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output wire o_cnt3,
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output wire o_cnt7,
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output wire o_ctrl_pc_en,
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output reg o_ctrl_jump,
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output wire o_ctrl_trap,
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input wire i_ctrl_misalign,
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output wire o_alu_shamt_en,
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input wire i_alu_sh_done,
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output wire o_dbus_cyc,
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output wire [1:0] o_mem_bytecnt,
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input wire i_mem_misalign,
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output reg o_cnt_done,
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output wire o_bufreg_hold);
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parameter [0:0] WITH_CSR = 1;
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wire cnt4;
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reg stage_two_req;
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reg [4:2] o_cnt;
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reg [3:0] o_cnt_r;
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//Update PC in RUN or TRAP states
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assign o_ctrl_pc_en = o_cnt_en & !o_init;
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assign o_mem_bytecnt = o_cnt[4:3];
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assign o_cnt0to3 = (o_cnt[4:2] == 3'd0);
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assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11));
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assign o_cnt0 = (o_cnt[4:2] == 3'd0) & o_cnt_r[0];
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assign o_cnt1 = (o_cnt[4:2] == 3'd0) & o_cnt_r[1];
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assign o_cnt2 = (o_cnt[4:2] == 3'd0) & o_cnt_r[2];
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assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3];
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assign cnt4 = (o_cnt[4:2] == 3'd1) & o_cnt_r[0];
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assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3];
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assign o_alu_shamt_en = (o_cnt0to3 | cnt4) & o_init;
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//Take branch for jump or branch instructions (opcode == 1x0xx) if
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//a) It's an unconditional branch (opcode[0] == 1)
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//b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (funct3[0] == 0) and ALU compare is true
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//c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (funct3[0] == 1) and ALU compare is false
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//Only valid during the last cycle of INIT, when the branch condition has
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//been calculated.
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wire take_branch = i_branch_op & (!i_cond_branch | (i_alu_cmp^i_bne_or_bge));
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//slt*, branch/jump, shift, load/store
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wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op;
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reg stage_two_pending;
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assign o_dbus_cyc = !o_cnt_en & stage_two_pending & i_mem_op & !i_mem_misalign;
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wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign);
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//Prepare RF for reads when a new instruction is fetched
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// or when stage one caused an exception (rreq implies a write request too)
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assign o_rf_rreq = i_ibus_ack | (stage_two_req & trap_pending);
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//Prepare RF for writes when everything is ready to enter stage two
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assign o_rf_wreq = ((i_shift_op & i_alu_sh_done & stage_two_pending) | (i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op))) & !trap_pending;
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assign o_rf_rd_en = i_rd_op & o_cnt_en & !o_init;
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//Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting
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assign o_bufreg_hold = !o_cnt_en & (stage_two_req | ~i_shift_op);
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always @(posedge i_clk) begin
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if (o_cnt_done)
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o_ctrl_jump <= o_init & take_branch;
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if (o_cnt_en)
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stage_two_pending <= o_init;
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o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2];
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//Need a strobe for the first cycle in the IDLE state after INIT
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stage_two_req <= o_cnt_done & o_init;
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if (i_rf_ready & !stage_two_pending)
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o_init <= two_stage_op & !o_pending_irq;
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if (o_cnt_done)
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o_init <= 1'b0;
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if (i_rf_ready)
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o_cnt_en <= 1'b1;
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if (o_cnt_done)
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o_cnt_en <= 1'b0;
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o_cnt <= o_cnt + {2'd0,o_cnt_r[3]};
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if (o_cnt_en)
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o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]};
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if (i_rst) begin
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o_cnt <= 3'd0;
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stage_two_pending <= 1'b0;
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o_ctrl_jump <= 1'b0;
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o_cnt_r <= 4'b0001;
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end
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end
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generate
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if (WITH_CSR) begin
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reg irq_sync;
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reg misalign_trap_sync;
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assign o_ctrl_trap = i_e_op | o_pending_irq | misalign_trap_sync;
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assign o_trap_taken = i_ibus_ack & o_ctrl_trap;
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always @(posedge i_clk) begin
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if (i_ibus_ack)
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irq_sync <= 1'b0;
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if (i_new_irq)
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irq_sync <= 1'b1;
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if (i_ibus_ack)
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o_pending_irq <= irq_sync;
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if (stage_two_req)
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misalign_trap_sync <= trap_pending;
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if (i_ibus_ack)
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misalign_trap_sync <= 1'b0;
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end // always @ (posedge i_clk)
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end else begin
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assign o_trap_taken = 0;
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assign o_ctrl_trap = 0;
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always @(*)
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o_pending_irq = 1'b0;
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end
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endgenerate
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endmodule
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