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629e6727f58b956c75b1dfeb0ada7c7563d04604
olofk.serv/rtl
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Olof Kindgren 629e6727f5 Move shamt to top byte in bufreg2 
Instead of shifting shamt all the way to bits 4:0, we just shift
8 steps. This saves some energy and allows us to be finished before
cnt_done.
2025-03-18 13:40:44 +01:00
..
serv_aligner.v
Delete trailing whitespace from RTL
2023-12-03 18:21:01 +01:00
serv_alu.v
Used named generate statements
2023-11-16 21:38:10 +01:00
serv_bufreg2.v
Move shamt to top byte in bufreg2
2025-03-18 13:40:44 +01:00
serv_bufreg.v
bufreg refactoring in preparation of qerv integration
2024-03-06 20:22:23 +01:00
serv_compdec.v
Delete trailing whitespace from RTL
2023-12-03 18:21:01 +01:00
serv_csr.v
Make CSR module 4-bit compatible
2024-10-05 11:27:51 +02:00
serv_ctrl.v
Support w=4 in serv_ctrl
2024-02-22 13:12:07 +01:00
serv_debug.v
Fix CSR write detection in debug module
2024-11-19 13:20:34 +01:00
serv_decode.v
Remove slt_or_branch control signal
2025-03-01 23:12:44 +01:00
serv_immdec.v
Used named generate statements
2023-11-16 21:38:10 +01:00
serv_mem_if.v
Move bytecnt to bufreg2
2025-03-01 23:12:44 +01:00
serv_rf_if.v
Support w=4 in serv_rf_if
2024-02-22 13:27:04 +01:00
serv_rf_ram_if.v
Add width-agnostic serv_rf_ram_if
2024-02-23 14:35:38 +01:00
serv_rf_ram.v
Rewrite serv_rf_ram_if
2023-06-22 15:48:25 +02:00
serv_rf_top.v
Add debug module
2024-10-13 22:24:00 +02:00
serv_state.v
Make branches, slt and left shifts one cycle faster
2025-03-01 23:12:44 +01:00
serv_synth_wrapper.v
Remove RVFI interface from synth wrapper
2022-12-25 20:05:52 +01:00
serv_top.v
Move shamt to top byte in bufreg2
2025-03-18 13:40:44 +01:00