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20 lines
314 B
Verilog
20 lines
314 B
Verilog
`default_nettype none
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module ser_add
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(
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input wire clk,
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input wire a,
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input wire b,
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input wire clr,
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output wire q,
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output wire o_v);
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reg c_r = 1'b0;
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assign o_v = (a&b | a&c_r | b&c_r);
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assign q = a ^ b ^ c_r;
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always @(posedge clk)
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c_r <= !clr & o_v;
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endmodule
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