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46 lines
1.0 KiB
Verilog
46 lines
1.0 KiB
Verilog
`default_nettype none
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module servant_te0802_clock_gen
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(input wire i_clk,
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output wire o_clk,
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output reg o_rst);
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wire clkfb;
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wire locked;
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reg locked_r;
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// Generate a 32 MHz clock from the 25MHz clock input
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MMCME4_ADV
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#(.DIVCLK_DIVIDE (1),
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.CLKFBOUT_MULT_F (48.000),
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.CLKOUT0_DIVIDE_F (37.5),
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.CLKIN1_PERIOD (40.0), //25MHz
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.STARTUP_WAIT ("FALSE"))
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mmcm
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(.CLKFBOUT (clkfb),
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.CLKFBOUTB (),
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.CLKOUT0 (o_clk),
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.CLKOUT0B (),
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.CLKOUT1 (),
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.CLKOUT1B (),
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.CLKOUT2 (),
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.CLKOUT2B (),
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.CLKOUT3 (),
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.CLKOUT3B (),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.CLKIN1 (i_clk),
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.CLKIN2 (1'b0),
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.CLKINSEL (1'b1),
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.LOCKED (locked),
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.PWRDWN (1'b0),
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.RST (1'b0),
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.CLKFBIN (clkfb));
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always @(posedge o_clk) begin
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locked_r <= locked;
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o_rst <= !locked_r;
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end
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endmodule
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