mirror of
https://github.com/olofk/serv.git
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98 lines
2.6 KiB
Verilog
98 lines
2.6 KiB
Verilog
`default_nettype none
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module serv_wrapper
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(
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input wb_clk,
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input wb_rst);
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parameter firmware = "firmware.hex";
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wire timer_irq;
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`include "wb_intercon.vh"
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localparam MEMORY_SIZE = 16384*4;
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reg [1023:0] firmware_file;
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initial
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if ($value$plusargs("firmware=%s", firmware_file)) begin
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$display("Loading RAM from %0s", firmware_file);
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$readmemh(firmware_file, ram.ram0.mem);
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end
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wb_ram
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#(/*.memfile (firmware),*/
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.depth (MEMORY_SIZE))
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ram
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(// Wishbone interface
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.wb_clk_i (wb_clk),
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.wb_rst_i (wb_rst),
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.wb_adr_i (wb_m2s_mem_adr[$clog2(MEMORY_SIZE)-1:0]),
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.wb_stb_i (wb_m2s_mem_stb),
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.wb_cyc_i (wb_m2s_mem_cyc),
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.wb_cti_i (wb_m2s_mem_cti),
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.wb_bte_i (wb_m2s_mem_bte),
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.wb_we_i (wb_m2s_mem_we) ,
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.wb_sel_i (wb_m2s_mem_sel),
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.wb_dat_i (wb_m2s_mem_dat),
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.wb_dat_o (wb_s2m_mem_dat),
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.wb_ack_o (wb_s2m_mem_ack),
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.wb_err_o ());
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testprint testprint
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(
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.i_wb_clk (wb_clk),
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.i_wb_dat (wb_m2s_testprint_dat),
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.i_wb_we (wb_m2s_testprint_we),
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.i_wb_cyc (wb_m2s_testprint_cyc),
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.i_wb_stb (wb_m2s_testprint_stb),
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.o_wb_ack (wb_s2m_testprint_ack));
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testhalt testhalt
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(
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.i_wb_clk (wb_clk),
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.i_wb_dat (wb_m2s_testhalt_dat),
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.i_wb_we (wb_m2s_testhalt_we),
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.i_wb_cyc (wb_m2s_testhalt_cyc),
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.i_wb_stb (wb_m2s_testhalt_stb),
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.o_wb_ack (wb_s2m_testhalt_ack));
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riscv_timer riscv_timer
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(.i_clk (wb_clk),
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.o_irq (timer_irq),
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.i_wb_adr (wb_m2s_timer_adr),
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.i_wb_stb (wb_m2s_timer_stb),
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.i_wb_cyc (wb_m2s_timer_cyc),
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.i_wb_we (wb_m2s_timer_we) ,
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.i_wb_sel (wb_m2s_timer_sel),
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.i_wb_dat (wb_m2s_timer_dat),
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.o_wb_dat (wb_s2m_timer_dat),
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.o_wb_ack (wb_s2m_timer_ack));
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serv_top
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#(.RESET_PC (32'h8000_0000))
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cpu
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(
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.clk (wb_clk),
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.o_ibus_adr (wb_m2s_cpu_ibus_adr),
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.o_ibus_cyc (wb_m2s_cpu_ibus_cyc),
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.o_ibus_stb (wb_m2s_cpu_ibus_stb),
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.i_ibus_rdt (wb_s2m_cpu_ibus_dat),
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.i_ibus_ack (wb_s2m_cpu_ibus_ack),
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.o_dbus_adr (wb_m2s_cpu_dbus_adr),
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.o_dbus_dat (wb_m2s_cpu_dbus_dat),
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.o_dbus_sel (wb_m2s_cpu_dbus_sel),
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.o_dbus_we (wb_m2s_cpu_dbus_we),
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.o_dbus_cyc (wb_m2s_cpu_dbus_cyc),
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.o_dbus_stb (wb_m2s_cpu_dbus_stb),
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.i_dbus_rdt (wb_s2m_cpu_dbus_dat),
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.i_dbus_ack (wb_s2m_cpu_dbus_ack));
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assign wb_m2s_cpu_ibus_dat = 32'd0;
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assign wb_m2s_cpu_ibus_we = 1'b0;
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assign wb_m2s_cpu_ibus_sel = 4'b1111;
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assign wb_m2s_cpu_ibus_cti = 3'b000;
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assign wb_m2s_cpu_ibus_bte = 2'b00;
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endmodule
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