mirror of
https://github.com/olofk/serv.git
synced 2026-01-24 19:11:48 +00:00
331 lines
9.9 KiB
Verilog
331 lines
9.9 KiB
Verilog
module serv_decode
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(
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input clk,
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input [31:0] i_wb_rdt,
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input i_wb_en,
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output o_ibus_active,
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output o_ctrl_en,
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output o_ctrl_jump,
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output o_ctrl_jalr,
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output o_ctrl_auipc,
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output reg o_ctrl_trap = 1'b0,
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output o_ctrl_mret,
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output o_rf_rd_en,
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output reg [4:0] o_rf_rd_addr,
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output o_rf_rs_en,
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output reg [4:0] o_rf_rs1_addr,
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output reg [4:0] o_rf_rs2_addr,
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output o_alu_en,
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output o_alu_init,
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output o_alu_sub,
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output reg o_alu_cmp_sel,
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output o_alu_cmp_neg,
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output reg o_alu_cmp_uns,
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input i_alu_cmp,
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output o_alu_shamt_en,
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output o_alu_sh_signed,
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output o_alu_sh_right,
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output reg [2:0] o_alu_rd_sel,
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output o_mem_en,
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output o_mem_cmd,
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output o_mem_init,
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output reg o_mem_dat_valid,
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input i_mem_busy,
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input i_mem_misalign,
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output o_csr_en,
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output reg [2:0] o_csr_sel,
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output reg [1:0] o_csr_source,
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output reg [2:0] o_funct3,
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output reg o_imm,
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output o_offset_source,
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output o_op_b_source,
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output [2:0] o_rd_source);
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`include "serv_params.vh"
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localparam [2:0]
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IDLE = 3'd0,
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INIT = 3'd1,
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MEM_INIT = 3'd3,
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MEM_WAIT = 3'd4,
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RUN = 3'd5;
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localparam [4:0]
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OP_LOAD = 5'b00000,
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OP_STORE = 5'b01000,
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OP_OPIMM = 5'b00100,
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OP_AUIPC = 5'b00101,
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OP_OP = 5'b01100,
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OP_LUI = 5'b01101,
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OP_BRANCH = 5'b11000,
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OP_JALR = 5'b11001,
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OP_JAL = 5'b11011,
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OP_SYSTEM = 5'b11100;
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reg [2:0] state = IDLE;
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reg [4:0] cnt = 5'd0;
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wire running;
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wire mem_op;
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wire shift_op;
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wire csr_op;
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wire jump_misaligned;
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reg signbit;
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assign o_ibus_active = (state == IDLE);
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assign mem_op = (opcode == OP_LOAD) | (opcode == OP_STORE);
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assign shift_op = ((opcode == OP_OPIMM) & (o_funct3[1:0] == 2'b01)) |
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((opcode == OP_OP ) & (o_funct3[1:0] == 2'b01));
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assign o_ctrl_en = running;
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assign o_ctrl_jump = (opcode == OP_JAL) |
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(opcode == OP_JALR) |
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((opcode == OP_BRANCH) & i_alu_cmp);
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assign o_ctrl_jalr = (opcode == OP_JALR);
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assign o_ctrl_auipc = (opcode == OP_AUIPC);
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assign o_ctrl_mret = (opcode == OP_SYSTEM) & imm[21] & !(|o_funct3);
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assign o_rf_rd_en = running & !o_ctrl_trap &
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(opcode != OP_STORE) &
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(opcode != OP_BRANCH);
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assign o_rf_rs_en = cnt_en;
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assign o_alu_en = cnt_en;
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assign o_alu_init = (state == INIT) |
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(state == MEM_INIT);
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assign o_alu_sub = (opcode == OP_OP) ? signbit /* ? 1'b1*/ :
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((opcode == OP_BRANCH) & (o_funct3 == 3'b100)) ? 1'b1 :
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((opcode == OP_BRANCH) & (o_funct3 == 3'b101)) ? 1'b1 :
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((opcode == OP_BRANCH) & (o_funct3 == 3'b110)) ? 1'b1 :
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((opcode == OP_OPIMM) & (o_funct3 == 3'b000)) ? 1'b0 :
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1'bx;
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assign o_alu_cmp_neg = (opcode == OP_BRANCH) & o_funct3[0];
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assign o_csr_en = ((opcode == OP_SYSTEM) & (|o_funct3) | o_ctrl_mret | o_ctrl_trap) & running;
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always @(o_funct3) begin
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casez (o_funct3)
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3'b00? : o_alu_cmp_sel = ALU_CMP_EQ;
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3'b01? : o_alu_cmp_sel = ALU_CMP_LT;
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3'b1?? : o_alu_cmp_sel = ALU_CMP_LT;
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default : o_alu_cmp_sel = 1'bx;
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endcase
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casez (o_funct3)
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3'b00? : o_alu_cmp_uns = 1'b0;
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3'b010 : o_alu_cmp_uns = 1'b0;
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3'b011 : o_alu_cmp_uns = 1'b1;
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3'b10? : o_alu_cmp_uns = 1'b0;
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3'b11? : o_alu_cmp_uns = 1'b1;
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default : o_alu_cmp_uns = 1'bx;
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endcase
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casez(o_funct3)
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3'b000 : o_alu_rd_sel = ALU_RESULT_ADD;
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3'b001 : o_alu_rd_sel = ALU_RESULT_SR;
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3'b01? : o_alu_rd_sel = ALU_RESULT_LT;
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3'b100 : o_alu_rd_sel = ALU_RESULT_XOR;
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3'b101 : o_alu_rd_sel = ALU_RESULT_SR;
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3'b110 : o_alu_rd_sel = ALU_RESULT_OR;
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3'b111 : o_alu_rd_sel = ALU_RESULT_AND;
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default : o_alu_rd_sel = 3'bxx;
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endcase
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casez(o_funct3[1:0])
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2'b01 : o_csr_source = CSR_SOURCE_EXT; //Check for x0
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2'b10 : o_csr_source = CSR_SOURCE_SET;
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2'b11 : o_csr_source = CSR_SOURCE_CLR;
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default : o_csr_source = 2'bxx;
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endcase
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if ((o_rf_rs1_addr == 5'd0) | o_ctrl_trap | o_ctrl_mret)
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o_csr_source = CSR_SOURCE_CSR;
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casez(imm[31:20])
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12'h305 : o_csr_sel = CSR_SEL_MTVEC;
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12'h341 : o_csr_sel = CSR_SEL_MEPC;
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12'h342 : o_csr_sel = CSR_SEL_MCAUSE;
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12'h343 : o_csr_sel = CSR_SEL_MTVAL;
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//12'hf14 : o_csr_sel = CSR_SEL_MHARTID;
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default : begin
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o_csr_sel = 3'bxxx;
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if (o_csr_en) begin
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$display("%0t: CSR %03h not implemented", $time, imm[31:20]);
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//#100 $finish;
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end
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end
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endcase
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if (o_ctrl_trap)
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o_csr_sel = CSR_SEL_MTVEC;
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if (o_ctrl_mret)
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o_csr_sel = CSR_SEL_MEPC;
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end
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assign o_alu_shamt_en = (cnt < 5) & ((state == INIT) |
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(state == MEM_INIT));
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assign o_alu_sh_signed = signbit;
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assign o_alu_sh_right = o_funct3[2];
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assign o_mem_en = mem_op & cnt_en;
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assign o_mem_cmd = (opcode == OP_STORE);
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assign o_mem_init = (state == MEM_INIT);
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assign jal_misalign = imm[21] & (opcode == OP_JAL);
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reg [4:0] opcode;
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reg [31:0] imm;
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always @(posedge clk) begin
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if (i_wb_en) begin
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o_rf_rd_addr <= i_wb_rdt[11:7];
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o_rf_rs1_addr <= i_wb_rdt[19:15];
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o_rf_rs2_addr <= i_wb_rdt[24:20];
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o_funct3 <= i_wb_rdt[14:12];
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signbit <= i_wb_rdt[30];
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opcode <= i_wb_rdt[6:2];
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imm <= i_wb_rdt;
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end
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end
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assign o_offset_source = (opcode == OP_JAL) ? OFFSET_SOURCE_IMM :
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(opcode == OP_AUIPC) ? OFFSET_SOURCE_IMM :
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(opcode == OP_BRANCH) ? OFFSET_SOURCE_IMM :
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(opcode == OP_JALR) ? OFFSET_SOURCE_IMM :
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1'bx;
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assign o_op_b_source = (opcode == OP_OPIMM) ? OP_B_SOURCE_IMM :
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(opcode == OP_BRANCH) ? OP_B_SOURCE_RS2 :
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(opcode == OP_OP) ? OP_B_SOURCE_RS2 :
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1'bx;
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always @(o_funct3, cnt, o_mem_init)
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if (o_mem_init)
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o_mem_dat_valid = 1'bx;
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else
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casez(o_funct3[1:0])
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2'b00 : o_mem_dat_valid = (cnt < 8);
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2'b01 : o_mem_dat_valid = (cnt < 16);
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2'b10 : o_mem_dat_valid = 1'b1;
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default: o_mem_dat_valid = 1'bx;
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endcase
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assign o_rd_source = (opcode == OP_JAL) ? RD_SOURCE_CTRL :
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(opcode == OP_OPIMM) ? RD_SOURCE_ALU :
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(opcode == OP_OP) ? RD_SOURCE_ALU :
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(opcode == OP_LUI) ? RD_SOURCE_IMM :
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(opcode == OP_AUIPC) ? RD_SOURCE_CTRL :
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(opcode == OP_JALR) ? RD_SOURCE_CTRL :
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(opcode == OP_SYSTEM) ? RD_SOURCE_CSR :
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(opcode == OP_LOAD) ? RD_SOURCE_MEM : 3'bxx;
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//31, cnt, 20, +20, +7, 7, 1'b0
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always @(cnt, opcode, imm) begin
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o_imm = 1'bx;
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if (opcode == OP_JAL)
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if (cnt > 19) o_imm = imm[31];
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else if (cnt > 11) o_imm = imm[cnt];
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else if (cnt > 10) o_imm = imm[20];
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else if (cnt > 0) o_imm = imm[cnt+20];
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else o_imm = 1'b0;
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else if ((opcode == OP_OPIMM) | (opcode == OP_JALR))
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if (cnt > 10) o_imm = imm[31];
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else o_imm = imm[cnt+20];
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else if ((opcode == OP_LUI) | (opcode == OP_AUIPC))
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if (cnt > 11) o_imm = imm[cnt];
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else o_imm = 1'b0;
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else if (opcode == OP_LOAD)
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if (cnt > 10) o_imm = imm[31];
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else o_imm = imm[cnt+20];
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else if (opcode == OP_BRANCH)
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if (cnt > 11) o_imm = imm[31];
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else if (cnt > 10) o_imm = imm[7];
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else if (cnt > 4) o_imm = imm[cnt+20];
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else if (cnt > 0) o_imm = imm[cnt+7];
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else o_imm = 1'b0;
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else if (opcode == OP_STORE)
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if (cnt > 10) o_imm = imm[31];
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else if (cnt > 4) o_imm = imm[cnt+20];
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else o_imm = imm[cnt+7];
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end
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reg go = 1'b0;
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always @(posedge clk)
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go <= i_wb_en;
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wire cnt_en =
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(state == RUN) |
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(state == INIT) |
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(state == MEM_INIT);
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wire cnt_done = cnt == 31;
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assign running = (state == RUN);
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always @(posedge clk) begin
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if (cnt_done)
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o_ctrl_trap <= i_mem_misalign;
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if (go)
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o_ctrl_trap <= jal_misalign;
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state <= state;
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case (state)
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IDLE : begin
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if (go)
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state <= (opcode == OP_BRANCH) ? INIT :
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(((opcode == OP_OPIMM) | (opcode == OP_OP))& (o_funct3[2:1] == 2'b01)) ? INIT :
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mem_op ? MEM_INIT :
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shift_op ? INIT : RUN;
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end
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INIT : begin
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if (cnt_done)
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state <= RUN;
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end
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MEM_INIT :
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if (cnt_done)
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state <= MEM_WAIT;
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MEM_WAIT :
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if (!i_mem_busy)
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state <= RUN;
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RUN : begin
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if (cnt_done)
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state <= IDLE;
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end
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default : state <= 3'bxxx;
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endcase
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cnt <= cnt + {4'd0,cnt_en};
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end
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`define SERV_DECODE_CHECKS
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`ifdef SERV_DECODE_CHECKS
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reg unknown_op = 1'b0;
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always @(opcode)
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if (i_wb_en) begin
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if (!((opcode == OP_LOAD) |
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(opcode == OP_STORE ) |
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(opcode == OP_OPIMM ) |
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(opcode == OP_AUIPC ) |
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(opcode == OP_OP ) |
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(opcode == OP_LUI ) |
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(opcode == OP_BRANCH) |
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(opcode == OP_JALR ) |
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(opcode == OP_SYSTEM ) |
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(opcode == OP_JAL ))) begin
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$display("Unknown opcode %b at %0t", opcode, $time);
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end // if ((opcode != OP_LOAD) |...
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end // if (i_wb_en)
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`endif
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endmodule
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