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41 lines
914 B
Verilog
41 lines
914 B
Verilog
`default_nettype none
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module testprint
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(
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input i_wb_clk,
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input [31:0] i_wb_dat,
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input i_wb_we,
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input i_wb_cyc,
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input i_wb_stb,
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output reg o_wb_ack /* verilator public */ = 1'b0);
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wire wb_en /* verilator public */;
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wire [7:0] ch /* verilator public */;
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assign ch = i_wb_dat[7:0];
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assign wb_en = i_wb_cyc & i_wb_stb;
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reg [1023:0] signature_file;
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integer f = 0;
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initial
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if ($value$plusargs("signature=%s", signature_file)) begin
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$display("Writing signature to %0s", signature_file);
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f = $fopen(signature_file, "w");
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end
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always @(posedge i_wb_clk) begin
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o_wb_ack <= 1'b0;
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if (wb_en & o_wb_ack) begin
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if (f)
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$fwrite(f, "%c", i_wb_dat[7:0]);
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$write("%c", i_wb_dat[7:0]);
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`ifndef VERILATOR
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$fflush();
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`endif
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end
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if (wb_en & !o_wb_ack)
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o_wb_ack <= 1'b1;
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end
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endmodule
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