mirror of
https://github.com/olofk/serv.git
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229 lines
7.2 KiB
Verilog
229 lines
7.2 KiB
Verilog
`default_nettype none
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module serv_decode
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(
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input wire clk,
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//Input
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input wire i_cnt_en,
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input wire [31:0] i_wb_rdt,
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input wire i_wb_en,
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input wire i_alu_cmp,
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//To state
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output wire o_take_branch,
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output wire o_e_op,
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output wire o_ebreak,
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output wire o_branch_op,
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output wire o_mem_op,
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output wire o_shift_op,
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output wire o_slt_op,
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//To bufreg
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output wire o_bufreg_loop,
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output wire o_bufreg_rs1_en,
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output wire o_bufreg_imm_en,
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//To ctrl
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output wire o_ctrl_jalr,
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output wire o_ctrl_jal_or_jalr,
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output wire o_ctrl_utype,
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output wire o_ctrl_pc_rel,
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output reg o_ctrl_mret,
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//To alu
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output wire o_alu_sub,
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output wire [1:0] o_alu_bool_op,
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output wire o_alu_cmp_eq,
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output wire o_alu_cmp_uns,
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output wire o_alu_sh_signed,
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output wire o_alu_sh_right,
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output reg [1:0] o_alu_rd_sel,
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//To RF
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output wire o_rf_rd_en,
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output reg [4:0] o_rf_rd_addr,
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output reg [4:0] o_rf_rs1_addr,
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output reg [4:0] o_rf_rs2_addr,
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//To mem IF
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output reg [2:0] o_funct3,
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output wire o_mem_cmd,
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//To CSR
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output wire o_csr_en,
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output reg [1:0] o_csr_addr,
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output wire o_csr_mstatus_en,
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output wire o_csr_mie_en,
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output wire o_csr_mcause_en,
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output wire [1:0] o_csr_source,
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output wire o_csr_d_sel,
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//To top
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output wire o_imm,
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output wire o_op_b_source,
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output wire o_rd_csr_en,
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output wire o_rd_alu_en,
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output wire o_rd_mem_en);
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`include "serv_params.vh"
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reg [4:0] opcode;
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reg [31:0] imm;
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reg op20;
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reg op21;
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reg op22;
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reg op26;
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reg imm30;
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wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]);
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assign o_mem_op = !opcode[4] & !opcode[2] & !opcode[0];
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assign o_shift_op = op_or_opimm & (o_funct3[1:0] == 2'b01);
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assign o_slt_op = op_or_opimm & (o_funct3[2:1] == 2'b01);
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assign o_branch_op = opcode[4] & !opcode[2];
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//Matches system opcodes except CSR accesses (o_funct3 == 0)
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//No idea anymore why the !op21 condition is needed here
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assign o_e_op = opcode[4] & opcode[2] & !op21 & !(|o_funct3);
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assign o_ebreak = op20;
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//jal,branch = imm
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//jalr = rs1+imm
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//mem = rs1+imm
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//shift = rs1
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assign o_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]);
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assign o_bufreg_imm_en = !opcode[2];
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//Loop bufreg contents for shift operations
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assign o_bufreg_loop = op_or_opimm;
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//Take branch for jump or branch instructions (opcode == 1x0xx) if
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//a) It's an unconditional branch (opcode[0] == 1)
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//b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (o_funct3[0] == 0) and ALU compare is true
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//c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (o_funct3[0] == 1) and ALU compare is false
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//Only valid during the last cycle of INIT, when the branch condition has
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//been calculated.
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wire o_take_branch = opcode[4] & !opcode[2] & (opcode[0] | (i_alu_cmp^o_funct3[0]));
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assign o_ctrl_utype = !opcode[4] & opcode[2] & opcode[0];
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assign o_ctrl_jalr = opcode[4] & (opcode[1:0] == 2'b01);
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assign o_ctrl_jal_or_jalr = opcode[4] & opcode[0];
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//True for jal, b* auipc
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//False for jalr, lui
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assign o_ctrl_pc_rel = (opcode[2:0] == 3'b000) |
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(opcode[1:0] == 2'b11) |
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(opcode[4:3] == 2'b00);
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wire mret = (i_wb_rdt[6] & i_wb_rdt[4] & i_wb_rdt[21] & !(|i_wb_rdt[14:12]));
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assign o_rf_rd_en = (opcode[2] |
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(!opcode[2] & opcode[4] & opcode[0]) |
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(!opcode[2] & !opcode[3] & !opcode[0]));
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assign o_alu_sub = opcode[3] & imm30/*alu_sub_r*/;
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/*
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300 0_000 mstatus RWSC
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304 0_100 mie SCWi
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305 0_101 mtvec RW
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340 1_000 mscratch
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341 1_001 mepc RW
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342 1_010 mcause R
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343 1_011 mtval
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344 1_100 mip CWi
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*/
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//true for mtvec,mscratch,mepc and mtval
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//false for mstatus, mie, mcause, mip
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wire csr_valid = op20 | (op26 & !op22 & !op21);
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//Matches system ops except eceall/ebreak
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wire csr_op = opcode[4] & opcode[2] & (|o_funct3);
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assign o_rd_csr_en = csr_op;
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assign o_csr_en = csr_op & csr_valid;
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assign o_csr_mstatus_en = csr_op & !op26 & !op22;
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assign o_csr_mie_en = csr_op & !op26 & op22 & !op20;
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assign o_csr_mcause_en = csr_op & op21 & !op20;
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assign o_csr_source = o_funct3[1:0];
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assign o_csr_d_sel = o_funct3[2];
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assign o_alu_cmp_eq = o_funct3[2:1] == 2'b00;
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assign o_alu_cmp_uns = (o_funct3[0] & o_funct3[1]) | (o_funct3[1] & o_funct3[2]);
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assign o_alu_sh_signed = imm30;
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assign o_alu_sh_right = o_funct3[2];
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assign o_mem_cmd = opcode[3];
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assign o_alu_bool_op = o_funct3[1:0];
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wire sign_bit = i_wb_rdt[31];
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wire [4:0] op_code = i_wb_rdt[6:2];
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wire btype = op_code[4] & !op_code[2] & !op_code[0];
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wire itype = (!op_code[3] & !op_code[0]) | (!op_code[2]&!op_code[1]&op_code[0]) | (!op_code[0]&op_code[2]);
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wire jtype = op_code[1];
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wire stype = op_code[3] & ~op_code[2] & ~op_code[4];
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wire utype = !op_code[4] & op_code[0];
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wire iorjtype = (op_code[0] & ~op_code[2]) | (op_code[2] & ~op_code[0]) | (~op_code[0] & ~op_code[3]);
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wire sorbtype = op_code[3:0] == 4'b1000;
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always @(posedge clk) begin
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casez(o_funct3)
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3'b000 : o_alu_rd_sel <= ALU_RESULT_ADD;
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3'b001 : o_alu_rd_sel <= ALU_RESULT_SR;
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3'b01? : o_alu_rd_sel <= ALU_RESULT_LT;
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3'b100 : o_alu_rd_sel <= ALU_RESULT_BOOL;
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3'b101 : o_alu_rd_sel <= ALU_RESULT_SR;
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3'b11? : o_alu_rd_sel <= ALU_RESULT_BOOL;
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endcase // casez (o_funct3)
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if (i_wb_en) begin
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o_rf_rd_addr <= i_wb_rdt[11:7];
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o_rf_rs1_addr <= i_wb_rdt[19:15];
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o_rf_rs2_addr <= i_wb_rdt[24:20];
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o_funct3 <= i_wb_rdt[14:12];
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imm30 <= i_wb_rdt[30];
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opcode <= i_wb_rdt[6:2];
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op20 <= i_wb_rdt[20];
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op21 <= i_wb_rdt[21];
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op22 <= i_wb_rdt[22];
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op26 <= i_wb_rdt[26];
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//Default to mtvec to have the correct CSR address loaded in case of trap
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o_csr_addr <= mret ? CSR_MEPC :
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(i_wb_rdt[26] & !i_wb_rdt[20]) ? CSR_MSCRATCH :
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(i_wb_rdt[26] & !i_wb_rdt[21]) ? CSR_MEPC :
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(i_wb_rdt[26]) ? CSR_MTVAL :
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CSR_MTVEC;
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o_ctrl_mret <= mret;
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imm[31] <= sign_bit;
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imm[30:20] <= utype ? i_wb_rdt[30:20] : {11{sign_bit}};
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imm[19:12] <= (utype | jtype) ? i_wb_rdt[19:12] : {8{sign_bit}};
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imm[11] <= btype ? i_wb_rdt[7] :
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utype ? 1'b0 :
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jtype ? i_wb_rdt[20] :
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sign_bit;
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imm[10:5] <= utype ? 6'd0 : i_wb_rdt[30:25];
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imm[4:1] <= (sorbtype) ? i_wb_rdt[11:8] :
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(iorjtype) ? i_wb_rdt[24:21] :
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4'd0;
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imm[0] <= itype ? i_wb_rdt[20] :
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stype ? i_wb_rdt[7] :
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1'b0;
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end
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if (i_cnt_en)
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imm <= {imm[0], imm[31:1]};
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end
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assign o_imm = imm[0];
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//0 (OP_B_SOURCE_IMM) when OPIMM
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//1 (OP_B_SOURCE_RS2) when BRANCH or OP
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assign o_op_b_source = opcode[3];
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assign o_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4];
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assign o_rd_mem_en = !opcode[2] & !opcode[4];
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endmodule
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