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12 lines
206 B
Verilog
12 lines
206 B
Verilog
module servant_gpio
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(
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input wire i_wb_clk,
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input wire i_wb_dat,
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input wire i_wb_cyc,
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output reg o_gpio);
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always @(posedge i_wb_clk)
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if (i_wb_cyc)
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o_gpio <= i_wb_dat;
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endmodule
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