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94 lines
2.9 KiB
Verilog
94 lines
2.9 KiB
Verilog
`default_nettype none
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module serv_mem_if
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#(parameter WITH_CSR = 1)
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(
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input wire i_clk,
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//State
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input wire i_en,
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input wire i_init,
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input wire i_cnt_done,
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input wire [1:0] i_bytecnt,
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input wire [1:0] i_lsb,
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output wire o_misalign,
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output wire o_sh_done,
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output wire o_sh_done_r,
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//Control
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input wire i_mem_op,
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input wire i_shift_op,
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input wire i_signed,
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input wire i_word,
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input wire i_half,
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//Data
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input wire i_op_b,
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output wire o_rd,
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//External interface
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output wire [31:0] o_wb_dat,
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output wire [3:0] o_wb_sel,
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input wire [31:0] i_wb_rdt,
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input wire i_wb_ack);
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reg signbit;
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reg [31:0] dat;
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wire [2:0] tmp = {1'b0,i_bytecnt}+{1'b0,i_lsb};
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wire dat_en = i_shift_op | (i_en & !tmp[2]);
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wire dat_cur =
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((i_lsb == 2'd3) & dat[24]) |
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((i_lsb == 2'd2) & dat[16]) |
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((i_lsb == 2'd1) & dat[8]) |
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((i_lsb == 2'd0) & dat[0]);
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wire dat_valid =
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i_word |
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(i_bytecnt == 2'b00) |
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(i_half & !i_bytecnt[1]);
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assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed);
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assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]);
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assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word;
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assign o_wb_sel[1] = (i_lsb == 2'b01) | i_word | (i_half & !i_lsb[1]);
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assign o_wb_sel[0] = (i_lsb == 2'b00);
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assign o_wb_dat = dat;
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/* The dat register has three different use cases for store, load and
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shift operations.
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store : Data to be written is shifted to the correct position in dat during
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init by dat_en and is presented on the data bus as o_wb_dat
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load : Data from the bus gets latched into dat during i_wb_ack and is then
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shifted out at the appropriate time to end up in the correct
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position in rd
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shift : Data is shifted in during init. After that, the six LSB are used as
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a downcounter (with bit 5 initially set to 0) that triggers
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o_sh_done and o_sh_done_r when they wrap around to indicate that
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the requested number of shifts have been performed
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*/
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wire [5:0] dat_shamt = (i_shift_op & !i_init) ?
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//Down counter mode
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dat[5:0]-1 :
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//Shift reg mode with optional clearing of bit 5
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{dat[6] & !(i_shift_op & i_cnt_done),dat[5:1]};
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assign o_sh_done = dat_shamt[5];
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assign o_sh_done_r = dat[5];
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always @(posedge i_clk) begin
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if (dat_en | i_wb_ack)
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dat <= i_wb_ack ? i_wb_rdt : {i_op_b, dat[31:7], dat_shamt};
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if (dat_valid)
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signbit <= dat_cur;
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end
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/*
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mem_misalign is checked after the init stage to decide whether to do a data
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bus transaction or go to the trap state. It is only guaranteed to be correct
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at this time
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*/
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assign o_misalign = WITH_CSR & ((i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word));
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endmodule
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