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13 lines
182 B
Core
13 lines
182 B
Core
CAPI=2:
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name : yosys:techlibs:ice40fork:0.7
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filesets:
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ice40_cells:
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files:
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- cells_sim.v : {file_type : verilogSource}
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targets:
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default:
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filesets : [ice40_cells]
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