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44 lines
1.1 KiB
Verilog
44 lines
1.1 KiB
Verilog
`default_nettype none
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module riscv_timer
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(input i_clk,
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output reg o_irq = 1'b0,
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input [31:0] i_wb_adr,
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input [31:0] i_wb_dat,
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input [3:0] i_wb_sel,
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input i_wb_we,
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input i_wb_cyc,
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input i_wb_stb,
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output reg [31:0] o_wb_dat,
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output reg o_wb_ack = 1'b0);
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reg [63:0] mtime = 64'd0;
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reg [63:0] mtimecmp = 64'd0;
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localparam [1:0]
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REG_MTIMELO = 2'd0,
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REG_MTIMEHI = 2'd1,
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REG_MTIMECMPLO = 2'd2,
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REG_MTIMECMPHI = 2'd3;
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always @(i_wb_adr)
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case (i_wb_adr[3:2])
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REG_MTIMELO : o_wb_dat = mtime[31:0];
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REG_MTIMEHI : o_wb_dat = mtime[63:32];
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REG_MTIMECMPLO : o_wb_dat = mtimecmp[31:0];
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REG_MTIMECMPHI : o_wb_dat = mtimecmp[63:32];
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endcase
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always @(posedge i_clk) begin
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o_wb_ack <= 1'b0;
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if (i_wb_cyc & i_wb_stb) begin
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o_wb_ack <= !o_wb_ack;
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if (i_wb_we & (i_wb_adr[3:2] == REG_MTIMECMPLO))
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mtimecmp[31:0] <= i_wb_dat;
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if (i_wb_we & (i_wb_adr[3:2] == REG_MTIMECMPHI))
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mtimecmp[63:32] <= i_wb_dat;
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end
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mtime <= mtime + 64'd1;
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o_irq <= (mtime >= mtimecmp);
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end
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endmodule
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