mirror of
https://github.com/olofk/serv.git
synced 2026-01-13 15:17:25 +00:00
394 lines
10 KiB
Verilog
394 lines
10 KiB
Verilog
`default_nettype none
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`define RISCV_FORMAL_NRET 1
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`define RISCV_FORMAL_XLEN 32
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`define RISCV_FORMAL_ILEN 32
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//`define RISCV_FORMAL_COMPRESSED
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`define RISCV_FORMAL_ALIGNED_MEM
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module serv_top
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(
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input wire clk,
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input wire i_rst,
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input wire i_timer_irq,
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`ifdef RISCV_FORMAL
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output reg rvfi_valid = 1'b0,
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output reg [63:0] rvfi_order = 64'd0,
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output reg [31:0] rvfi_insn = 32'd0,
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output reg rvfi_trap = 1'b0,
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output reg rvfi_halt = 1'b0,
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output reg rvfi_intr = 1'b0,
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output reg [1:0] rvfi_mode = 2'b11,
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output reg [4:0] rvfi_rs1_addr,
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output reg [4:0] rvfi_rs2_addr,
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output reg [31:0] rvfi_rs1_rdata,
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output reg [31:0] rvfi_rs2_rdata,
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output reg [4:0] rvfi_rd_addr,
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output reg [31:0] rvfi_rd_wdata,
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output reg [31:0] rvfi_pc_rdata,
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output reg [31:0] rvfi_pc_wdata,
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output reg [31:0] rvfi_mem_addr,
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output reg [3:0] rvfi_mem_rmask,
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output reg [3:0] rvfi_mem_wmask,
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output reg [31:0] rvfi_mem_rdata,
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output reg [31:0] rvfi_mem_wdata,
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`endif
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output wire [31:0] o_ibus_adr,
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output wire o_ibus_cyc,
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input wire [31:0] i_ibus_rdt,
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input wire i_ibus_ack,
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output wire [31:0] o_dbus_adr,
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output wire [31:0] o_dbus_dat,
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output wire [3:0] o_dbus_sel,
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output wire o_dbus_we ,
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output wire o_dbus_cyc,
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input wire [31:0] i_dbus_rdt,
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input wire i_dbus_ack);
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`include "serv_params.vh"
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wire [4:0] rd_addr;
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wire [4:0] rs1_addr;
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wire [4:0] rs2_addr;
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wire rd_alu_en;
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wire rd_mem_en;
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wire ctrl_rd;
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wire alu_rd;
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wire mem_rd;
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wire csr_rd;
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wire rd;
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wire ctrl_en;
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wire ctrl_pc_en;
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wire ctrl_misalign;
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wire jump;
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wire jalr;
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wire jal_or_jalr;
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wire utype;
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wire mret;
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wire imm;
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wire trap;
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wire [4:0] cnt;
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wire [3:0] cnt_r;
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wire cnt_done;
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wire [2:0] funct3;
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wire bufreg_hold;
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wire bufreg_imm_en;
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wire bufreg_loop;
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wire alu_en;
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wire alu_init;
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wire alu_sub;
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wire [1:0] alu_bool_op;
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wire alu_cmp_sel;
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wire alu_cmp_neg;
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wire alu_cmp_uns;
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wire alu_cmp;
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wire alu_shamt_en;
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wire alu_sh_signed;
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wire alu_sh_right;
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wire alu_sh_done;
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wire [1:0] alu_rd_sel;
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wire rf_ready;
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wire rs1;
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wire rs2;
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wire rs_en;
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wire rd_en;
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wire op_b_source;
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wire op_b;
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wire mem_en;
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wire mem_cmd;
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wire [1:0] mem_bytecnt;
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wire mem_init;
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wire mem_misalign;
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wire bad_pc;
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wire bad_adr;
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wire csr_mstatus_en;
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wire csr_mie_en;
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wire csr_mtvec_en;
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wire csr_mip_en;
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wire csr_mscratch_en;
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wire csr_mepc_en;
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wire csr_mcause_en;
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wire csr_mtval_en;
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wire [1:0] csr_source;
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wire csr_imm;
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wire csr_d_sel;
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wire [3:0] mcause;
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parameter RESET_PC = 32'd8;
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wire lui;
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wire timer_irq_en;
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serv_decode decode
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(
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.clk (clk),
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.i_rst (i_rst),
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.i_mtip (i_timer_irq),
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.i_timer_irq_en (timer_irq_en),
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.i_wb_rdt (i_ibus_rdt),
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.i_wb_en (o_ibus_cyc & i_ibus_ack),
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.i_rf_ready (rf_ready | i_dbus_ack),
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.o_cnt (cnt),
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.o_cnt_r (cnt_r),
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.o_cnt_done (cnt_done),
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.o_bufreg_hold (bufreg_hold),
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.o_bufreg_imm_en (bufreg_imm_en),
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.o_bufreg_loop (bufreg_loop),
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.o_ctrl_en (ctrl_en),
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.o_ctrl_pc_en (ctrl_pc_en),
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.o_ctrl_jump (jump),
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.o_ctrl_jalr (jalr),
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.o_ctrl_jal_or_jalr (jal_or_jalr),
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.o_ctrl_utype (utype),
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.o_ctrl_lui (lui),
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.o_ctrl_trap (trap),
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.o_ctrl_mret (mret),
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.i_ctrl_misalign(ctrl_misalign),
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.o_funct3 (funct3),
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.o_alu_en (alu_en),
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.o_alu_init (alu_init),
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.o_alu_sub (alu_sub),
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.o_alu_bool_op (alu_bool_op),
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.o_alu_cmp_sel (alu_cmp_sel),
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.o_alu_cmp_neg (alu_cmp_neg),
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.o_alu_cmp_uns (alu_cmp_uns),
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.i_alu_cmp (alu_cmp),
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.o_alu_shamt_en (alu_shamt_en),
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.o_alu_sh_signed (alu_sh_signed),
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.o_alu_sh_right (alu_sh_right),
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.i_alu_sh_done (alu_sh_done),
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.o_alu_rd_sel (alu_rd_sel),
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.o_rf_rs_en (rs_en),
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.o_rf_rd_en (rd_en),
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.o_rf_rd_addr (rd_addr),
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.o_rf_rs1_addr (rs1_addr),
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.o_rf_rs2_addr (rs2_addr),
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.o_mem_en (mem_en),
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.o_mem_cmd (mem_cmd),
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.o_mem_init (mem_init),
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.o_mem_bytecnt (mem_bytecnt),
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.i_mem_misalign (mem_misalign),
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.o_csr_mstatus_en (csr_mstatus_en),
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.o_csr_mie_en (csr_mie_en),
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.o_csr_mtvec_en (csr_mtvec_en),
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.o_csr_mip_en (csr_mip_en),
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.o_csr_mscratch_en (csr_mscratch_en),
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.o_csr_mepc_en (csr_mepc_en),
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.o_csr_mcause_en (csr_mcause_en),
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.o_csr_mtval_en (csr_mtval_en),
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.o_csr_source (csr_source),
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.o_csr_mcause (mcause),
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.o_csr_imm (csr_imm),
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.o_csr_d_sel (csr_d_sel),
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.o_imm (imm),
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.o_op_b_source (op_b_source),
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.o_rd_alu_en (rd_alu_en),
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.o_rd_mem_en (rd_mem_en));
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wire [1:0] lsb;
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wire [31:0] bufreg_out;
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assign o_dbus_adr = {bufreg_out[31:2], 2'b00};
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serv_bufreg bufreg
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(
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.i_clk (clk),
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.i_rst (i_rst),
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.i_cnt (cnt),
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.i_cnt_r (cnt_r),
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.i_en (!(bufreg_hold | o_dbus_cyc)),
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.i_clr (!mem_en),
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.i_loop (bufreg_loop),
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.i_rs1 (rs1),
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.i_rs1_en (1'b1),
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.i_imm (imm),
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.i_imm_en (bufreg_imm_en),
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.o_lsb (lsb),
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.o_reg (bufreg_out),
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.o_q (bad_adr));
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serv_ctrl
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#(.RESET_PC (RESET_PC))
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ctrl
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(
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.clk (clk),
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.i_rst (i_rst),
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.i_en (ctrl_en),
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.i_pc_en (ctrl_pc_en),
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.i_cnt (cnt),
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.i_cnt_r (cnt_r),
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.i_cnt_done (cnt_done),
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.i_jump (jump),
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.i_offset (imm),
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.i_rs1 (rs1),
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.i_jalr (jalr),
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.i_jal_or_jalr (jal_or_jalr),
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.i_utype (utype),
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.i_lui (lui),
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.i_trap (trap | mret),
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.i_csr_pc (csr_rd),
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.o_rd (ctrl_rd),
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.o_bad_pc (bad_pc),
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.o_misalign (ctrl_misalign),
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.o_ibus_adr (o_ibus_adr),
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.o_ibus_cyc (o_ibus_cyc),
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.i_ibus_ack (i_ibus_ack));
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assign rd = (ctrl_rd ) |
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(rd_alu_en & alu_rd ) |
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(csr_rd ) |
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(rd_mem_en & mem_rd);
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assign op_b = (op_b_source == OP_B_SOURCE_IMM) ? imm : rs2;
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serv_alu alu
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(
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.clk (clk),
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.i_rst (i_rst),
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.i_en (alu_en),
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.i_rs1 (rs1),
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.i_op_b (op_b),
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.i_buf (bad_adr), //FIXME
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.i_init (alu_init),
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.i_cnt_done (cnt_done),
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.i_sub (alu_sub),
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.i_bool_op (alu_bool_op),
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.i_cmp_sel (alu_cmp_sel),
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.i_cmp_neg (alu_cmp_neg),
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.i_cmp_uns (alu_cmp_uns),
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.o_cmp (alu_cmp),
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.i_shamt_en (alu_shamt_en),
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.i_sh_right (alu_sh_right),
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.i_sh_signed (alu_sh_signed),
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.o_sh_done (alu_sh_done),
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.i_rd_sel (alu_rd_sel),
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.o_rd (alu_rd));
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serv_regfile regfile
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(
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.i_clk (clk),
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.i_rst (i_rst),
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.i_go (i_ibus_ack),
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.o_ready (rf_ready),
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.i_rd_en (rd_en),
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.i_rd_addr (rd_addr),
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.i_rd (rd),
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.i_rs1_addr (rs1_addr),
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.i_rs2_addr (rs2_addr),
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.o_rs1 (rs1),
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.o_rs2 (rs2));
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serv_mem_if mem_if
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(
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.i_clk (clk),
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.i_rst (i_rst),
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.i_en (mem_en),
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.i_init (mem_init),
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.i_cmd (mem_cmd),
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.i_bytecnt (mem_bytecnt),
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.i_funct3 (funct3),
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.i_rs2 (rs2),
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.o_rd (mem_rd),
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.i_lsb (lsb),
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.o_misalign (mem_misalign),
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.i_trap (trap),
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//External interface
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.o_wb_dat (o_dbus_dat),
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.o_wb_sel (o_dbus_sel),
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.o_wb_we (o_dbus_we ),
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.o_wb_cyc (o_dbus_cyc),
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.i_wb_rdt (i_dbus_rdt),
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.i_wb_ack (i_dbus_ack));
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serv_csr csr
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(
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.i_clk (clk),
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.i_cnt (cnt),
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.i_cnt_r (cnt_r),
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.i_mtip (i_timer_irq),
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.o_timer_irq_en ( timer_irq_en),
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.i_mstatus_en (csr_mstatus_en),
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.i_mie_en (csr_mie_en ),
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.i_mtvec_en (csr_mtvec_en ),
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.i_mip_en (csr_mip_en ),
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.i_mscratch_en (csr_mscratch_en),
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.i_mepc_en (csr_mepc_en ),
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.i_mcause_en (csr_mcause_en ),
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.i_mtval_en (csr_mtval_en ),
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.i_csr_source (csr_source),
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.i_trap (trap),
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.i_pc (o_ibus_adr[0]),
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.i_mtval (mem_misalign ? bad_adr : bad_pc),
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.i_mcause (mcause),
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.i_d (csr_d_sel ? csr_imm : rs1),
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.o_q (csr_rd));
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`ifdef RISCV_FORMAL
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reg [31:0] pc = RESET_PC;
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always @(posedge clk) begin
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rvfi_valid <= cnt_done & ctrl_pc_en;
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rvfi_order <= rvfi_order + rvfi_valid;
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if (o_ibus_cyc & i_ibus_ack)
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rvfi_insn <= i_ibus_rdt;
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if (rd_en)
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rvfi_rd_wdata <= {rd,rvfi_rd_wdata[31:1]};
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if (cnt_done & ctrl_pc_en) begin
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rvfi_pc_rdata <= pc;
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if (!rd_en)
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rvfi_rd_addr <= 5'd0;
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if (!rd_en | !(|rd_addr))
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rvfi_rd_wdata <= 32'd0;
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end
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rvfi_trap <= trap;
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if (rvfi_valid) begin
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rvfi_trap <= 1'b0;
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pc <= rvfi_pc_wdata;
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end
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rvfi_halt <= 1'b0;
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rvfi_intr <= 1'b0;
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rvfi_mode <= 2'd3;
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if (rf_ready) begin
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rvfi_rs1_addr <= rs1_addr;
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rvfi_rs2_addr <= rs2_addr;
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rvfi_rd_addr <= rd_addr;
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end
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if (rs_en) begin
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rvfi_rs1_rdata <= {rs1,rvfi_rs1_rdata[31:1]};
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rvfi_rs2_rdata <= {rs2,rvfi_rs2_rdata[31:1]};
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end
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if (i_dbus_ack) begin
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rvfi_mem_addr <= o_dbus_adr;
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rvfi_mem_rmask <= o_dbus_we ? 4'b0000 : o_dbus_sel;
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rvfi_mem_wmask <= o_dbus_we ? o_dbus_sel : 4'b0000;
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rvfi_mem_rdata <= i_dbus_rdt;
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rvfi_mem_wdata <= o_dbus_dat;
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end
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if (i_ibus_ack) begin
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rvfi_mem_rmask <= 4'b0000;
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rvfi_mem_wmask <= 4'b0000;
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end
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end
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always @(o_ibus_adr)
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rvfi_pc_wdata <= o_ibus_adr;
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`endif
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endmodule
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