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https://github.com/olofk/serv.git
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52 lines
1017 B
Verilog
52 lines
1017 B
Verilog
`default_nettype none
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module serv_clock_gen
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(
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input i_clk,
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output o_clk,
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output o_rst);
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parameter PLL = "NONE";
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generate
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if (PLL == "ICE40_CORE") begin
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wire locked;
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SB_PLL40_CORE
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#(`include "pll.vh")
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pll
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(
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.LOCK(locked),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(i_clk),
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.PLLOUTCORE(o_clk));
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reg [1:0] rst_reg;
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always @(posedge o_clk)
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rst_reg <= {!locked, rst_reg[1]};
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assign o_rst = rst_reg[0];
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end else if (PLL == "ICE40_PAD") begin
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wire locked;
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SB_PLL40_PAD
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#(`include "pll.vh")
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pll
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(
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.LOCK(locked),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.PACKAGEPIN (i_clk),
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.PLLOUTCORE(o_clk));
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reg [1:0] rst_reg;
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always @(posedge o_clk)
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rst_reg <= {!locked, rst_reg[1]};
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assign o_rst = rst_reg[0];
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end else begin
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assign o_clk = i_clk;
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reg [4:0] rst_reg = 5'b11111;
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always @(posedge o_clk)
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rst_reg <= {1'b0, rst_reg[4:1]};
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assign o_rst = rst_reg[0];
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end
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endgenerate
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endmodule
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