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58 lines
1.3 KiB
Verilog
58 lines
1.3 KiB
Verilog
`default_nettype none
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module serv_alu
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(
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input wire clk,
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//State
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input wire i_en,
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input wire i_cnt0,
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output wire o_cmp,
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//Control
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input wire i_sub,
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input wire [1:0] i_bool_op,
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input wire i_cmp_eq,
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input wire i_cmp_sig,
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input wire [2:0] i_rd_sel,
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//Data
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input wire i_rs1,
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input wire i_op_b,
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input wire i_buf,
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output wire o_rd);
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wire result_add;
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reg cmp_r;
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wire add_cy;
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reg add_cy_r;
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//Sign-extended operands
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wire rs1_sx = i_rs1 & i_cmp_sig;
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wire op_b_sx = i_op_b & i_cmp_sig;
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wire add_b = i_op_b^i_sub;
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assign {add_cy,result_add} = i_rs1+add_b+add_cy_r;
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wire result_lt = rs1_sx + ~op_b_sx + add_cy;
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wire result_eq = !result_add & (cmp_r | i_cnt0);
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assign o_cmp = i_cmp_eq ? result_eq : result_lt;
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localparam [15:0] BOOL_LUT = 16'h8E06;//And, Or, 0, xor
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wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, i_op_b}];
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assign o_rd = i_buf |
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(i_rd_sel[0] & result_add) |
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(i_rd_sel[1] & cmp_r & i_cnt0) |
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(i_rd_sel[2] & result_bool);
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always @(posedge clk) begin
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add_cy_r <= i_en ? add_cy : i_sub;
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if (i_en)
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cmp_r <= o_cmp;
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end
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endmodule
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