mirror of
https://github.com/olofk/serv.git
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131 lines
3.6 KiB
Verilog
131 lines
3.6 KiB
Verilog
module serv_decode
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(
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input clk,
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input [31:0] i_i_rd_dat,
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input i_i_rd_vld,
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output reg o_i_rd_rdy = 1'b1,
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output o_ctrl_en,
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output o_ctrl_jump,
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output [2:0] o_funct3,
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output o_rf_rd_en,
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output [4:0] o_rf_rd_addr,
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output o_rf_rs_en,
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output [4:0] o_rf_rs1_addr,
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output [4:0] o_rf_rs2_addr,
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output o_mem_en,
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output o_mem_init,
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output o_mem_dat_valid,
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input i_mem_busy,
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output reg o_imm,
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output o_offset_source,
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output o_op_b_source,
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output [1:0] o_rd_source);
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`include "serv_params.vh"
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localparam [1:0]
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IDLE = 2'd0,
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MEM_INIT = 2'd1,
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MEM_WAIT = 2'd2,
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RUN = 2'd3;
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localparam [4:0]
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OP_LOAD = 5'b00000,
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OP_OPIMM = 5'b00100,
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OP_LUI = 5'b01101,
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OP_JAL = 5'b11011;
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reg [1:0] state = 2'd0;
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reg [4:0] cnt = 5'd0;
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wire running;
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wire mem_op;
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assign mem_op = (opcode == OP_LOAD);
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assign o_ctrl_en = running;
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assign o_ctrl_jump = (opcode == OP_JAL);
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assign o_rf_rd_en = running & ((opcode == OP_JAL) |
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(opcode == OP_OPIMM) |
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(opcode == OP_LUI));
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assign o_rf_rs_en = (running & (opcode == OP_OPIMM)) |
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(state == MEM_INIT);
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assign o_mem_en = mem_op & cnt_en;
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assign o_mem_init = (state == MEM_INIT);
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assign o_rf_rd_addr = i_i_rd_dat[11:7];
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assign o_funct3 = i_i_rd_dat[14:12];
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assign o_rf_rs1_addr = i_i_rd_dat[19:15];
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assign o_rf_rs2_addr = i_i_rd_dat[24:20];
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assign o_offset_source = (opcode == OP_JAL) ? OFFSET_SOURCE_IMM : 1'b0;
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assign o_op_b_source = (opcode == OP_OPIMM) ? OP_B_SOURCE_IMM : 1'b0;
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assign o_mem_dat_valid = (o_funct3[1:0] == 2'b00) ? cnt < 8 :
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(o_funct3[1:0] == 2'b01) ? cnt < 16 : 1'b1;
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wire [4:0] opcode = i_i_rd_dat[6:2];
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assign o_rd_source = (opcode == OP_JAL) ? RD_SOURCE_CTRL :
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(opcode == OP_OPIMM) ? RD_SOURCE_ALU :
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(opcode == OP_LUI) ? RD_SOURCE_IMM : 2'b00;
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always @(cnt, opcode) begin
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o_imm = 1'bx;
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if (opcode == OP_JAL)
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if (cnt > 19) o_imm = i_i_rd_dat[31];
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else if (cnt > 11) o_imm = i_i_rd_dat[cnt];
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else if (cnt > 10) o_imm = i_i_rd_dat[20];
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else if (cnt > 0) o_imm = i_i_rd_dat[cnt+20];
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else o_imm = 1'b0;
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else if (opcode == OP_OPIMM)
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if (cnt > 10) o_imm = i_i_rd_dat[31];
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else o_imm = i_i_rd_dat[cnt+20];
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else if (opcode == OP_LUI)
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if (cnt > 11) o_imm = i_i_rd_dat[cnt];
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else o_imm = 1'b0;
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else if (opcode == OP_LOAD)
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if (cnt > 10) o_imm = i_i_rd_dat[31];
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else o_imm = i_i_rd_dat[cnt+20];
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end
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wire go = i_i_rd_vld & o_i_rd_rdy;
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wire cnt_en = (state == RUN) | (state == MEM_INIT);
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wire cnt_done = cnt == 31;
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assign running = (state == RUN);
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always @(posedge clk) begin
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state <= state;
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case (state)
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IDLE : begin
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if (go)
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state <= mem_op ? MEM_INIT : RUN;
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end
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MEM_INIT :
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if (cnt_done)
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state <= MEM_WAIT;
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MEM_WAIT :
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if (!i_mem_busy)
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state <= RUN;
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RUN : begin
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if (cnt_done)
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state <= IDLE;
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end
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endcase
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cnt <= cnt + {4'd0,cnt_en};
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if (go) begin
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o_i_rd_rdy <= 1'b0;
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end else if (cnt_done & (state == RUN)) begin
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o_i_rd_rdy <= 1'b1;
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end
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end
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endmodule
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